Image features are broadly used in embedded computer vision applications, from object detection and tracking to motion estimation and 3D reconstruction. Efficient feature extraction and description are crucial due to ...
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ISBN:
(纸本)9782839918442
Image features are broadly used in embedded computer vision applications, from object detection and tracking to motion estimation and 3D reconstruction. Efficient feature extraction and description are crucial due to the real-time requirements of such applications over a constant stream of input data. High-speed computation typically comes at the cost of high power dissipation, yet embedded systems are often highly power constrained, making discovery of power-aware solutions especially critical for these systems. In this paper, we present a power and performance evaluation of three low cost feature detection and description algorithms implemented on various embedded systems (embedded CPUs, GPUs and FPGAs). We show that FPGAs in particular offer attractive solutions for both performance and power and describe several design techniques utilized to accelerate feature extraction and description algorithms on low-cost Zynq SoC FPGAs.
Nowadays, FPGAs are integrated in high-performance computing systems, servers, or even used as accelerators in System-on-Chip (SoC) platforms. Since the execution is performed in hardware, FPGA gives much higher perfo...
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This paper proposes an effective three-dimensional compressive sensing method for the phased array weather radar (PAWR), which is capable of three-dimensional observation with spatially and temporally high resolution....
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ISBN:
(纸本)9781538615652
This paper proposes an effective three-dimensional compressive sensing method for the phased array weather radar (PAWR), which is capable of three-dimensional observation with spatially and temporally high resolution. Because of the large amount of observation data, which is approximately 1 gigabyte per minute, data compression is an essential technology to conduct a network observation by multiple PAWRs. Even though many conventional studies applied compressive sensing (CS) to weather radar measurements, their reconstruction quality should be further improved. To this end, we define a cost function for a three-dimensional recovery exploiting not only local similarity but also global redundancy of weather radar measurements. Since the cost function is convex, we can derive an efficient algorithm based on the standard convex optimization techniques. Simulation results show that the proposed method achieves normalized errors less than 10% for 25% compression ratio with outperforming conventional two-dimensional methods.
Embedded System Reconfigurability has begun since few years thanks to the FPGA capabilities. Many approaches and methodologies have been adopted in literature. Several tools were proposed to designers, but a big luck ...
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Circuit structural recovering is a technique that derives functional blocks using low-level description. Its value resides chiefly in recovering information of high-level description from a project of integrated circu...
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Circuit structural recovering is a technique that derives functional blocks using low-level description. Its value resides chiefly in recovering information of high-level description from a project of integrated circuit when its design is lost, Intellectual Property (IP) synthesized in field-programmable Gate Array (FPGA), and in others cases when its structure is desirable. Furthermore, many SAT (Boolean satisfiability problem) solvers take advantage of information they can recover and knowledge of the domain problem to improve their processing (e.g. Algorithm Portfolios and Combinational Equivalence Checking). Being so, recovering circuit structural information is a key ingredient for improvements in formal verification using SAT solvers;a helpful step of structural recovering is the functional block identification. Taking an image generated from a circuit's CNF description, and considering CNN's maturity on the image recognition domain, we are able to map a macro functional block with a very high accuracy. The main contributions of this paper are the following: (i) We propose the innovative identification of functional blocks through images (ii) We implemented the system based on CNN using TensorFlow (iii) Our experimental results obtained an accuracy over 80%.
field-programmable Gate Arrays (FPGAs) benefit from the most advanced CMOS technology nodes, in order to meet the increasing demands of high performance and low power digital integrated circuits. This makes them susce...
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ISBN:
(纸本)9782839918442
field-programmable Gate Arrays (FPGAs) benefit from the most advanced CMOS technology nodes, in order to meet the increasing demands of high performance and low power digital integrated circuits. This makes them susceptible to various reliability challenges at nano-scale. In this paper, we focus on aging degradation of the Look-up table (LUT) on FPGAs. We have characterized the delay degradation of LUT depending on the duty cycle of stress vectors. We have identified also that the duty cycle affects strongly the fall and moderately the rise delay of LUT due to the NBTI aging mechanism. Furthermore, a semi-empirical model of the degradation of LUT timing due to NBTI depending on the time and the duty cycle of stress vector has been investigated in this work. This model can be used to predict the degradation of a complex circuit implemented in a FPGA, and especially the risk of timing violations due to NBTI aging.
This paper proposes an effective method for frequency spectrum estimation using multi-channel co-prime sampling. Previous work has adopted a multi-channel sampling system to sense sparse signals, but its model suffers...
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ISBN:
(纸本)9781538615652
This paper proposes an effective method for frequency spectrum estimation using multi-channel co-prime sampling. Previous work has adopted a multi-channel sampling system to sense sparse signals, but its model suffers from the grid mismatch problem and the average sampling rate is high due to the redundancy among different channels. In this paper, we design a multi-channel co-prime sampling scheme to further reduce the average sampling rate. Then we incorporate the grid-free method called super-resolution for continuous support recovery which is not influenced by the discretized grids. Meanwhile, we also give a new support set reduction criterion which further decreases the cardinality of candidate frequency support set and the optimum choice of co-prime sampling rate. Numerical results demonstrate the correctness of our proposed method.
We consider the problem of determining the asymptotic order of the Gelfand numbers of mixed-(quasi)norm,4 embeddings l(p)(b)(l(q)(d)) -> l(b)(r)(l(d)(u)) given that p <= r and q <= u, with emphasis on cases w...
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ISBN:
(纸本)9781538615652
We consider the problem of determining the asymptotic order of the Gelfand numbers of mixed-(quasi)norm,4 embeddings l(p)(b)(l(q)(d)) -> l(b)(r)(l(d)(u)) given that p <= r and q <= u, with emphasis on cases with p <= 1 and/or q <= 1. These cases turn out to be related to structured sparsity. We obtain sharp bounds in a number of interesting parameter constellations. Our new matching bounds for the Gelfand numbers of the embeddings of l(1)(b) (l(2)(d)) and l(2)(b) (l(1)(d)) into l(2)(b) (l(2)(d)) imply optimality assertions for the recovery of block-sparse and sparse-in-levels vectors, respectively. In addition, we apply the sharp estimates for l(p)(b)(l(q)(d))-spacesto obtain new two-sided estimates for the Gelfand numbers of multivariate Besov space embeddings in regimes of small mixed smoothness. It turns out that in some particular cases these estimates show the same asymptotic behaviour as in the univariate situation. In the remaining cases they differ at most by a log log factor from the univariate bound.
High Level Synthesis (HLS) relies on the use of synthesis pragmas to generate digital designs meeting a set of specifications. However, the selection of a set of pragmas depends largely on designer experience and know...
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ISBN:
(纸本)9781538630938
High Level Synthesis (HLS) relies on the use of synthesis pragmas to generate digital designs meeting a set of specifications. However, the selection of a set of pragmas depends largely on designer experience and knowledge of the target architecture and digital design. Existing automated methods of pragma selection are very limited in scope and capability to analyze complex design descriptions in high-level languages to be synthesized using HLS. In this paper, we propose COMBA, a comprehensive model-based analysis framework capable of analyzing the effects of a multitude of pragmas related to functions, loops and arrays in the design description using pluggable analytical models, a recursive data collector (RDC) and a metricguided design space exploration algorithm (MGDSE). When compared with HLS tools like Vivado HLS, COMBA reports an average error of around 1% in estimating performance, while taking only a few seconds for analysis of Polybench benchmark applications and a few minutes for real-life applications like JPEG, Seidel and Rician. The synthesis pragmas recommended by COMBA result in an average 100x speed-up in performance for the analyzed applications, which establishes COMBA as a superior alternative to current state-of-the-art approaches.
Configuration scrubbing is a technique used for repairing Single Event Upsets (SEUs) within the configuration memory of an FPGA. Scrubbing approaches have been developed using hardware external to the FPGA communicati...
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ISBN:
(纸本)9782839918442
Configuration scrubbing is a technique used for repairing Single Event Upsets (SEUs) within the configuration memory of an FPGA. Scrubbing approaches have been developed using hardware external to the FPGA communicating through a configuration port and using hardware within the FPGA by communicating with an internal configuration port (ICAP). More recent FPGAs such as the Xilinx Zynq 7-Series SoCs provide internal programmable processors that can configure the FPGA logic very rapidly using an internal Processor Configuration Access Port (PCAP). These SoC/FPGAs also provide automatic internal scrubbing through the use of high-speed readback and configuration error correction. This paper presents a novel form of FPGA configuration scrubbing for the Zynq-7000 SoC family by combining the highspeed PCAP configuration port with internal scrubbing. This novel scrubber corrects single-bit upsets in several microseconds and detects these upsets in 8 ms.
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