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检索条件"任意字段=International Conference on Field Programmable Logic and Applications"

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Design of a passive damped filter for harmonic reduction in multilevel inverters used in PV applications

Design of a passive damped filter for harmonic reduction in ...

引用

IEEE Power India conference

作者： Meenakshi Jayaraman V.T. Sreedevi Research Scholar School of Electrical Engineering VIT University Chennai India Professor School of Electrical Engineering VIT University Chennai India

ISBN: (纸本)9781538673409;9781538673393

A passive filter is connected at the output of a voltage source inverter in standalone and grid connected applications to reduce harmonics. This paper presents a parameter design procedure of a passive LC filter containing a damping resistor for a five level inverter. The work aims to improve the output waveforms of the inverter and reduce the total harmonic distortion content on its output waveforms. The design is carried out with an objective to provide better attenuation of switching frequency harmonics and effective suppression of resonant peaks. All equations derived are simple and accurate which provides insight into design of passive LC filter with resistance damping without cumbersome algorithms. This work uses a modified methodology to arrive at the value of damping resistance for harmonic reduction with minimum losses. The modified method considers quality factor, resonant peaking, harmonic attenuation rate and power loss in the damping branch to select the resistance value. Simulation and experimental results are included to analyse the harmonic distortion on the output waveforms. Experiments have been conducted on a five level cascaded H-Bridge inverter set up. The modulation scheme is implemented on a FPGA platform using SPARTAN 3E-XCS250E controller. A very good agreement is seen between the experimental and simulation results of the developed filter design. The results prove the effectiveness of the resistive damped passive filter for multilevel inverters.

关键词： Power harmonic filters Inverters Passive filters Harmonic analysis Damping Resistance field programmable gate arrays

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Low-Latency TCP/IP Stack for Data Center applications 26

Low-Latency TCP/IP Stack for Data Center Applications

引用

26th international conference on field-programmable logic and applications (FPL)

作者： Sidler, David Istvan, Zsolt Alonso, Gustavo Swiss Fed Inst Technol Syst Grp Dept Comp Sci Zurich Switzerland

ISBN: (纸本)9782839918442

TCP/IP is widely used both in the Internet as well as in data centers. The protocol makes very few assumptions about the underlying network and provides useful guarantees such as reliable transmission, in-order delivery, or control flow. The price for this functionality is complexity, latency, and computational overhead, which is especially pronounced in software implementations. While for Internet communication this is acceptable, the overhead is too high in data centers. In this paper, we explore how to optimize a TCP/IP stack running on an FPGA for data center applications with an emphasis on data processing (e.g., key value stores). Using a key-value store and a low-latency consensus protocol implemented on an FPGA as an example of the requirements that arise in data centers, we provide an extensive analysis of the overheads of TCP/IP and the solutions that can be adopted to minimize such an overhead. The proposed optimized TCP/IP stack minimizes tail latencies (a key metric in distributed data processing) and is efficiently implemented so as to be able to share the FPGA with application logic.

关键词： field programmable gate arrays (FPGA)

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Behavioral Verification of Service Component Architecture 26

Behavioral Verification of Service Component Architecture

引用

26th IEEE international conference on Enabling Technologies - Infrastructure for Collaborative Enterprises (WETICE)

作者： Chargui, Wael Rouis, Taoufik Sakka Kmimech, Mourad Bhiri, Mohamed Tahar Sliman, Layth Raddaoui, Badran Univ Tunis El Manar UR OASIS ENIT Tunis Tunisia Univ Manouba Crystal Lab ENSI Manouba 2010 Tunisia Pole Technol Sfax Lab Miracl ISIMS Sfax Tunisia Efrei Ecole Ingenieur Gen Informat Villejuif France Telecom Sudparis 9 Rue Charles Fourier F-91000 Evry France

ISBN: (纸本)9781538617595

Currently, much research looks at treating the behavior properties beginning with the architectural design phase in SCA (Software Component Architectures) based applications. In this paper, we propose to map SCA onto the Wright ADL in order to verify the behavioral consistency of SCA software architectures. To achieve this goal, we suggest translating this source software architecture into a Wright configuration. Using Wr2fdr tool, this Wright configuration can be automatically translated to a CSP specification acceptable by the FDR2 model-checker.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Interpretability Indices for Hierarchical Fuzzy Systems

Interpretability Indices for Hierarchical Fuzzy Systems

引用

IEEE international conference on Fuzzy Systems (FUZZ-IEEE)

作者： Razak, T. R. Garibaldi, J. M. Wagner, C. Pourabdollah, A. Soria, D. Univ Nottingham Sch Comp Sci Lab Uncertainty Data & Decis Making LUCID Intelligent Modelling & Anal Grp Nottingham England Michigan Technol Univ ICC Houghton MI 49931 USA Univ Westminster Dept Comp Sci London England

ISBN: (纸本)9781509060344

Hierarchical fuzzy systems (HFSs) have been shown to have the potential to improve interpretability of fuzzy logic systems (FLSs). In recent years, a variety of indices have been proposed to measure the interpretability of FLSs such as the Nauck index and Fuzzy index. However, interpretability indices associated with HFSs have not so far been discussed. The structure of HFSs, with multiple layers, subsystems, and varied topologies, is the main challenge in constructing interpretability indices for HFSs. Thus, the comparison of interpretability between FLSs and HFSs-even at the index level-is still subject to open discussion. This paper begins to address these challenges by introducing extensions to the FLS Nauck and Fuzzy interpretability indices for HFSs. Using the proposed indices, we explore the concept of interpretability in relation to the different structures in FLSs and HFSs. Initial experiments on benchmark datasets show that based on the proposed indices, HFSs with equivalent function to FLSs produce higher indices, i.e. are more interpretable than their corresponding FLSs.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Accelerating Recurrent Neural Networks in Analytics Servers: Comparison of FPGA, CPU, GPU, and ASIC 26

Accelerating Recurrent Neural Networks in Analytics Servers:...

引用

26th international conference on field-programmable logic and applications (FPL)

作者： Nurvitadhi, Eriko Sim, Jaewoong Sheffield, David Mishra, Asit Krishnan, Srivatsan Marr, Debbie Intel Corp Santa Clara CA 95051 USA

ISBN: (纸本)9782839918442

Recurrent neural networks (RNNs) provide state-of-the-art accuracy for performing analytics on datasets with sequence (e.g., language model). This paper studied a state-of-the-art RNN variant, Gated Recurrent Unit (GRU). We first proposed memoization optimization to avoid 3 out of the 6 dense matrix vector multiplications (SGEMVs) that are the majority of the computation in GRU. Then, we study the opportunities to accelerate the remaining SGEMVs using FPGAs, in comparison to 14-nm ASIC, GPU, and multi-core CPU. Results show that FPGA provides superior performance/Watt over CPU and GPU because FPGA's on-chip BRAMs, hard DSPs, and reconfigurable fabric allow for efficiently extracting fine-grained parallelisms from small/medium size matrices used by GRU. Moreover, newer FPGAs with more DSPs, on-chip BRAMs, and higher frequency have the potential to narrow the FPGA-ASIC efficiency gap.

关键词： field programmable gate arrays (FPGA)

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High Performance Space Computing with System-on-Chip Instrument Avionics for Space-based Next Generation Imaging Spectrometers (NGIS)

High Performance Space Computing with System-on-Chip Instrum...

引用

NASA/ESA conference on Adaptive Hardware and Systems (AHS)

作者： Didier Keymeulen Simon Shin Jason Riddley Matthew Klimesh Aaron Kiely Elliott Liggett Peter Sullivan Michael Bernas Hamid Ghossemi Greg Flesch Michael Cheng Sam Dolinar David Dolman Kevin Roth Chris Holyoake Ken Crocker Adam Smith NASA Jet Propulsion Laboratory California Institute of Technology Pasadena CA USA Alpha Data Inc.

The emergent technology of system-on-chip (SoC) devices promises lighter, smaller, cheaper, and more capable and reliable space electronic systems that could help to unveil some of the most treasured secrets in our universe. This technology is an improvement over the technology that is currently used in space applications, which lags behind state-of-the-art commercial-off-the-shelf (COTS) equipment by several generations. SoC technology integrates all computational power required by next-generation space exploration science instruments onto a single chip. This presentation will describe a Xilinx Zynqbased data acquisition, cloud-screening and compression computing system that has been developed at the Jet Propulsion Laboratory (JPL) foJJPL's Next Generation Imaging Spectrometers (NGIS). The Xilinx Zynq-based Alpha Data hardware assembly fits into a 120mm by 190m by 40mm assembly and uses 9 watts at peak performance. The computing element is a Xilinx Zynq Z7045Q which includes a Kintex-7 FPGA (equivalent to 3 RAD Virtex5 FPGAs in terms of logic cell resources) and dual-core ARM Cortex-A9 Processors (equivalent to 10 RAD750 Power PCs in term of processing capability).

关键词： Hardware Hyperspectral imaging field programmable gate arrays Aerospace electronics Instruments Image coding Software

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Overcoming Resource Underutilization in Spatial CNN Accelerators 26

Overcoming Resource Underutilization in Spatial CNN Accelera...

引用

26th international conference on field-programmable logic and applications (FPL)

作者： Shen, Yongming Ferdman, Michael Milder, Peter SUNY Stony Brook Stony Brook NY 11794 USA

ISBN: (纸本)9782839918442

Convolutional neural networks (CNNs) are revolutionizing a variety of machine learning tasks, but they present significant computational challenges. Recently, FPGA-based accelerators have been proposed to improve the speed and efficiency of CNNs. Current approaches construct an accelerator optimized to maximize the overall throughput of iteratively computing the CNN layers. However, this approach leads to dynamic resource underutilization because the same accelerator is used to compute CNN layers of radically varying dimensions. We present a new CNN accelerator design that improves the dynamic resource utilization. Using the same FPGA resources, we build multiple accelerators, each specialized for specific CNN layers. Our design achieves 1.3x higher throughput than the state of the art when evaluating the convolutional layers of the popular AlexNet CNN on a Xilinx Virtex-7 FPGA.

关键词： field programmable gate arrays (FPGA)

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GraVF: A Vertex-Centric Distributed Graph Processing Framework on FPGAs 26

GraVF: A Vertex-Centric Distributed Graph Processing Framewo...

引用

26th international conference on field-programmable logic and applications (FPL)

作者： Engelhardt, Nina So, Hayden Kwok-Hay Univ Hong Kong Dept Elect & Elect Engn Hong Kong Hong Kong Peoples R China

ISBN: (纸本)9782839918442

FPGAs are promising platforms to efficiently execute distributed graph algorithms. Unfortunately, they are notoriously hard to program, especially when the problem size and system complexity increases. In this paper, we propose GraVF, a high-level design framework for distributed graph processing on FPGAs. It leverages the vertex-centric paradigm, which is naturally distributed and requires the user to define only very small kernels and their associated message semantics for the target application. The user design may subsequently be elaborated and compiled to the target system automatically by the framework. To demonstrate the flexibility and capabilities of the proposed framework, 4 graph algorithms with distinct requirements have been implemented, namely breadth-first search, PageRank, single source shortest path, and connected component. Results show that the proposed framework is capable of producing FPGA designs with performance comparable to similar custom designs while requiring only minimal input from the user.

关键词： field programmable gate arrays (FPGA)

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Fuzzy Sliding Mode Method for Speed regulation of a Dual Star Induction Machine Drive fed by Multi-level Inverters

Fuzzy Sliding Mode Method for Speed regulation of a Dual Sta...

引用

international conference on Applied Smart Systems (ICASS)

作者： Elyazid Zaidi Khoudir Marouani Hakim Bouadi Abd Elhalim Kassel Larafi Bentouhami Elkheir Merabet Ecole Militaire Polytechnique LCM-UER-ELT Bordj El-Bahri Algiers Algeria Faculty of Sciences & Technology University of Bordj Bou Arreridj Algiers Algeria Department of Electrical Engineering University of Batna Algiers Algeria Department of Electrical Engineering University of Bordj Bou Arreridj Algiers Algeria

ISBN: (纸本)9781538668672;9781538668665

This paper presents a robust fuzzy-sliding mode control (FSC) technique for speed control of a drive system based on dual star induction machine (DISM). The machine is fed by two multilevel voltage source inverters (MLVSI) and its control is achieved using a fuzzy-sliding mode controller combined with the indirect field oriented control (IFOC) technique. The MLVSI technology has recently emerged and applied to DC-AC conversion to obtain sinusoidal waveform and to fulfill different applications constraints such as: high power conversion, power segmentation and power control. The FSC has many advantages, such as: fast response good robustness, high efficiency and suppressed chattering phenomenon. The presented study is validated by a series of simulation results showing the main responses of the drive system in case of different operating conditions. Also, the proposed FSC controller is compared to the classical PI controller and demonstrated superior performances.

关键词： Inverters Power capacitors Stators Regulators Sliding mode control Fuzzy logic Induction machines

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Improved Resource Sharing for FPGA DSP Blocks 26

Improved Resource Sharing for FPGA DSP Blocks

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26th international conference on field-programmable logic and applications (FPL)

作者： Ronak, Bajaj Fahmy, Suhaib A. Nanyang Technol Univ Sch Comp Sci & Engn Singapore Singapore Univ Warwick Sch Engn Coventry W Midlands England

ISBN: (纸本)9782839918442

Sharing multi-cycle hardware blocks like the DSP48E1 primitive in Xilinx FPGAs can result in significant resource savings, but complicates scheduling. For high-throughput, DSP blocks must be pipelined, which results in a high initiation interval (II) for resource shared implementations. In this paper, we propose a resource reduction technique that minimises DSP block usage while also offering improved II over traditional approaches. This is integrated in a high-level tool which takes datapath descriptions in C and generates synthesisable Verilog RTL with different levels of resource sharing. We demonstrate significantly improved throughput compared to traditional resource sharing while achieving resource reduction compared to resource unconstrained and HLS implementations. The approach explores an otherwise infeasible design space between resource unconstrained and traditional resource sharing methods.

关键词： field programmable gate arrays (FPGA)

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