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检索条件"任意字段=International Conference on Field Programmable Logic and Applications"

共 16795 条记录，以下是4651-4660 订阅

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Counting in the Dark: DNS Caches Discovery and Enumeration in the Internet 47

Counting in the Dark: DNS Caches Discovery and Enumeration i...

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47th IEEE/IFIP Annual international conference on Dependable Systems and Networks (DSN)

作者： Klein, Amit Shulman, Haya Waidner, Michael Fraunhofer Inst Secure Informat Technol Darmstadt Germany

ISBN: (纸本)9781538605424

Domain Name System (DNS) is a fundamental element of the Internet providing lookup services for end users as well as for a multitude of applications, systems and security mechanisms that depend on DNS, such as anti-spam defences, routing security, firewalls, certificates and more. Caches constitute a critical component of DNS, allowing to improve efficiency and reduce latency and traffic in the Internet. Understanding the behaviour, configurations and topologies of caches in the DNS platforms in the Internet is important for efficiency and security of Internet users and services. In this work we present methodologies for efficiently discovering and enumerating the caches of the DNS resolution platforms in the Internet. We apply our techniques and methodologies for studying caches in popular DNS resolution platforms in the Internet. Our study includes networks of major ISPs, enterprises and professionally managed open DNS resolvers. The results of our Internet measurements shed light on architectures and configurations of the caches in DNS resolution platforms.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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A Proposal for a Magnetostriction-Assisted All-Spin logic Device 75

A Proposal for a Magnetostriction-Assisted All-Spin Logic De...

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75th Annual Device Research conference (DRC)

作者： Iraei, Rouhollah Mousavi Dutta, Sourav Manipatruni, Sasikanth Nikonov, Dmitri E. Young, Ian A. Heron, John T. Naeemi, Azad Georgia Inst Technol Sch Elect & Comp Engn Atlanta GA 30332 USA Intel Corp Components Res Grp Hillsboro OR 97124 USA Univ Michigan Dept Mat Sci & Engn Ann Arbor MI 48109 USA

ISBN: (纸本)9781509063284

As scaling CMOS devices is approaching its fundamental limits, a new direction of research has emerged to study beyond-CMOS spintronic devices that use electronic spin as their state variable, offering new and enhanced functionalities. Due to low operating voltage, non-volatility, and efficient implementation of majority gate, a novel spin-based device, all-spin logic (ASL), has been widely studied for applications including interconnects [1], pattern recognition systems [2], and Boolean gates [3]. However, ASL relies on a non-local spin valve (NLSV) structure with the connection to ground being close to the input magnet to ensure non-reciprocity. Thus, a large fraction of injected spins is shunted to ground without ever reaching the output magnet. In addition, supply clocking is envisioned to reduce energy dissipation [3]. Even then, a 32-bit addition by ASL compared to that by CMOS, requires 5 orders of magnitude more energy. In this paper, we propose a novel device that uses voltage-controlled strain-mediated magnetization switching [4] and spin transfer torque (STT) to perform the first and second 90⁰ of switching, respectively. The STT is created in a conventional spin valve instead of the NLSV structure used in ASL. Hence, the wasteful shunt path to ground is eliminated. Non-reciprocity is ensured through a clocking scheme in which the input and output magnets are oriented along the stable easy axis and the meta-stable saddle point of energy profile, respectively. It has been shown that the deterministic switching of a magnet from a saddle point is more efficient in terms of delay and energy and affected less by thermal noise [5], [6]. The device can be cascaded in a domino logic scheme, Fig. 1 a, by performing the first 90⁰ switching for all cascaded logic gates simultaneously; therefore, the overall delay of a more complicated circuit like a 32-bit adder significantly improves.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Blind Gain and Phase Calibration for Low-Dimensional or Sparse Signal Sensing via Power Iteration 12

Blind Gain and Phase Calibration for Low-Dimensional or Spar...

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12th international conference on Sampling Theory and applications (SAMPTA)

作者： Li, Yanjun Lee, Kiryung Bresler, Yoram Univ Illinois Dept ECE Urbana IL 61801 USA Univ Illinois CSL Urbana IL 61801 USA Georgia Inst Technol Sch ECE Atlanta GA 30332 USA

ISBN: (纸本)9781538615652

Blind gain and phase calibration (BGPC) is a bilinear inverse problem involving the determination of unknown gains and phases of the sensing system, and the unknown signal, jointly. BGPC arises in numerous applications, e.g., blind albedo estimation in inverse rendering, synthetic aperture radar autofocus, and sensor array auto-calibration. In some cases, sparse structure in the unknown signal alleviates the ill-posedness of BGPC. Recently there has been renewed interest in solutions to BGPC with careful analysis of error bounds. In this paper, we formulate BGPC as an eigenvalue/eigenvector problem, and propose to solve it via power iteration, or in the sparsity or joint sparsity case, via truncated power iteration. Under certain assumptions, the unknown gains, phases, and the unknown signal can be recovered simultaneously. Numerical experiments show that power iteration algorithms work not only in the regime predicted by our main results, but also in regimes where theoretical analysis is limited. We also show that our power iteration algorithms for BGPC compare favorably with competing algorithms in adversarial conditions, e.g., with noisy measurement or with a bad initial estimate.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Design and Simulation of DPLL for FPGA Based Carrier Recovery Loop: PSK Receiver for Digital Satellite Communication

Design and Simulation of DPLL for FPGA Based Carrier Recover...

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IEEE international conference on Recent Trends in Electronics, Information & Communication Technology

作者： Rahul Rathod Pinakin Thaker Nilima Kolhare Government College of Engineering Aurangabad Aurangabad India Sci/Eng. SG Space Applications Centre Indian Space Research Organisation Ahmedabad India

ISBN: (数字)9781538624401

ISBN: (纸本)9781538624418

In this paper, we present the digital phase locked loop (DPLL) model for FPGA based carrier recovery loop in Phase Shift Keying (PSK) receiver. The main design goal is to transform S-domain Analog PLL to the Z-domain of DPLL without redesigning model. Additionally, this paper present design, analysis, mathematical modelling, mathematical analysis of algorithms which are Impulse-Invariance Algorithm (IIA), Zero-Order Hold Algorithm (ZOHA), Bilinear Transform Algorithm (BLTA) and Matched Pole-Zero Algorithm (MPZA). Design of DPLL which is based on all discretization algorithms are presented and simulated using MATLAB 13a and Xilinx ISE 14.7 system generator. We present the comparative analysis of simulation from which it is found that BLTA is the most celebrated algorithm. Moreover, The BLTA based structure of DPLL adapts the response to allow the DPLL to lock faster than other discretized DPLL. Analysis and steps of the discretization algorithms is discussed and results of MATLAB and Xilinx ISE 14.7 system generator are presented for FPGAs and ASICs based platform.

关键词： Phase locked loops Mathematical model Approximation algorithms Transforms Heuristic algorithms field programmable gate arrays Matlab

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Measure Twice and Cut Once: Robust Dynamic Voltage Scaling for FPGAs 26

Measure Twice and Cut Once: Robust Dynamic Voltage Scaling f...

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26th international conference on field-programmable logic and applications (FPL)

作者： Ahmed, Ibrahim Zhao, Shuze Trescases, Olivier Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9782839918442

Although dynamic voltage scaling (DVS) is a popular power reduction solution that has been widely used by processors and ASICs, it is still not commercially adopted by FPGAs. A unique feature of FPGAs that leads to challenges in adopting DVS is that the critical path and hence the minimum safe V-dd depends on the configured application. We present a robust DVS technique that solves these challenges. For each application, we generate a calibration table (CT) that stores the actual failing points of that application on a specific FPGA, under various operating conditions. This CT is used to scale V-dd while the application is running to guarantee safe operation with minimal power consumption. We develop an automated tool (FRoC) that ensures a Fast-Robust-Calibration of the FPGA to any application using it. FRoC ensures that the calibration process is invisible to FPGA users and does not add any extra manual steps to the design process. We show that our proposed DVS technique achieves a 33% total power reduction on two large applications.

关键词： field programmable gate arrays (FPGA)

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Robotic Vision Assembly using FPGA

Robotic Vision Assembly using FPGA

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IEEE international conference on Automatica (ICA-ACCA)

作者： M. Peña-Cabrera A.H. Jiménez R. Osorio V. Lomas I.J. López G. Lefranc IIMAS Universidad Nacional Autónoma de México CDMX Posgrado Ingeniería Universidad Nacional Autónoma de México CDMX CINVESTAV Saltillo Coahuila México UCV Chile

An artificial visión system based in the BOF method implemented in a FPGA device is presented to locate and recognize rigid work pieces within an experimental workspace area, previous location is not known by a manipulator robotized element in order to grasp it and perform an assembly process (peg in hole) in real time. As the processor element a Nexys 4 development electronic FPGA card is used with Hardware Description Language (HDL) platform for its programming, and the OV7670 camera from OmniVision is used as the imaege acquisition device. Data is acquired, conditioned and processed to get information about location and feature recognition characteristics for the assembly process within an experimental manufacturing cell environment containing an educative robot manipulator of 6DOF. Two methods were used for comparison results resulting 50% success assembly for the first one when only using primitive descriptors of area an centroid and 96% success when BOF method was using. An assembly process was performed integrating the method in a single FPGA device. Having performed real time image acquisition and processing actions, the results shows the possibility of using this method for concurrent and fast assembly applications.

关键词： field programmable gate arrays Robot sensing systems Service robots Visualization Robotic assembly Performance evaluation

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Binary time domain reflectometry: a simpler and more efficient way of diagnosing defects in wired networks

Binary time domain reflectometry: a simpler and more efficie...

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international Automatic Testing conference, AUTOTESTCON

作者： Fabrice Auzanneau CEA CEA Sac lay France

Today, the most efficient methods for wired networks diagnosis are based on reflectometry: they can detect hard (i.e. open/short circuits) and soft defects (i.e. insulation damage, hot spots or rust), either permanent or intermittent, and provide their location. This is an important information for maintenance operators who can focus repair in a shorter time. The possibility of monitoring the wires health using specifically designed reflectometry methods offers interesting opportunities for preventive maintenance. Electronic implementations of such methods are mostly based on the use of programmable logic digital systems, such as FPGA or microcontrollers, both for probe signals generation and measured signals analysis. But the cables have a pure analog behavior, therefore these systems are connected to additional costly devices such as digital to analog and analog to digital converters. These components have a direct impact on the systems performances: a higher sampling rate means a better defects location accuracy, but implies a higher cost. A higher resolution enables to detect lower signature defects but requires more memory and computing power for data processing. This paper presents a new purely binary reflectometry method using a simpler electronic architecture and quicker signal analysis, and showing better performances than standard methods (in terms of defect location accuracy, processing speed and memory requirement) at a lower cost. Equivalent detection performances are shown, and the new simplified electronic architecture enables to take advantage of all the digital resources, such as a higher clock frequency than that of most available converters, thus naturally improving the location accuracy. As the conversion components are not required anymore, the consumption and cost of the system is drastically reduced. Performance comparison is presented and an innovative process for the reflectogram computation is introduced, which enables a drastic reduction o

关键词： Standards Power cables Time-domain analysis field programmable gate arrays Signal resolution AWGN Probes

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Processor Specific Green Counter Based on HSTL IO Standards Design on 90nm FPGA

Processor Specific Green Counter Based on HSTL IO Standards ...

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international conference on Internet of Things: Smart Innovation and Usages (IoT-SIU)

作者： Sushant Shekhar Ritik Raj Ajay Kumar Gaurav Verma Pushpendra Raj Department of Electronics and Communication Engineering Tula’s Institute Dehradun India Department of Electronics and Communication Engineering JIIT NOIDA India

ISBN: (纸本)9781538638330

In today's world with a specific end goal to broaden the battery life and pick up in term of convey ability, there is dependably an examination hole in low power processor plan. Keeping in mind the end goal to finish low power processor configuration venture, there is have to re-plan every single piece of processor with low power methods. Determination of vitality effective I/O standard is additionally assuming a critical part in vitality proficient outline. In this work, we are utilizing High Speed Transceiver logic (HSTL). This design is implemented in verilog on Zedboard Zynq evaluation kit using vivado 2016.2 tool. Here, we utilize six diverse HSTL IO Standards. These are: HSTL_I, HSTL_II, HSTL_III, HSTL_III_18, HSTL__III_DCI, and HSTL_II_18. For all these IO standard, we checked our Green Counter design on 1.0GHz, 2.5GHz, 3.5GHz, 3.7GHz, 3.9GHz and 4.0GHz processor frequency. With different frequency scaling, we are optimizing 11.22% I/O power, 79.3% clock power and 100% signal power by running our design with 1GHz frequency. As we increased switched to 4.0GHZ to 1.0GHZ frequency we show there is huge amount power conumption. Among all these HSTL_III_DCI consumes maximum power while HSTL_I consumes minimum.

关键词： Clocks Standards field programmable gate arrays Power dissipation Switches Energy efficiency Power demand

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Bayesian Inference implemented on FPGA with Stochastic Bitstreams for an Autonomous Robot 26

Bayesian Inference implemented on FPGA with Stochastic Bitst...

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26th international conference on field-programmable logic and applications (FPL)

作者： Fernandes, Hugo Awais Aslam, M. Lobo, Jorge Ferreira, Joao Filipe Dias, Jorge Univ Coimbra ISR P-3000 Coimbra Portugal Univ Coimbra ISR DEEC P-3000 Coimbra Portugal Khalifa Univ Abu Dhabi U Arab Emirates

ISBN: (纸本)9782839918442

This paper presents an FPGA implementation of a machine performing exact Bayesian inference using stochastic bitstreams. We revisited stochastic computing, not to perform better computations with unreliable hardware, but to perform approximate computations with less hardware. The underlying trade-off is between precision and computation time. An automatic design of probabilistic machines that compute soft inferences with an arithmetic based on stochastic bitstreams is presented. The computation tree provided by a Bayesian inference software is used to define the stochastic circuit. Tests were performed and results presented concerning accuracy and resource usage of the stochastic computing implementation of Bayesian machines performing exact inference. An application example is given of a Bayesian sensorimotor system that performs obstacle avoidance for an autonomous robot, fully implemented on an FPGA. Some conclusions were drawn on the followed approach, providing insights for future implementations.

关键词： field programmable gate arrays (FPGA)

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An Implementation method of the Box Filter on FPGA 26

An Implementation method of the Box Filter on FPGA

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26th international conference on field-programmable logic and applications (FPL)

作者： Wang, Sichao Maruyama, Tsutomu Univ Tsukuba Syst & Informat Engn 1-1-1 Tennodai Tsukuba Ibaraki Japan

ISBN: (纸本)9782839918442

The box filter is widely used in image processing. Its computational complexity is low, and many other filters can be realized by using different size box filters. The implementation method of the box filter that is widely used in the software programs requires an array to store data, the size of which is filter size x image width. This array often limits the feasibility of the box filter on FPGA, because its size is proportional to the image width. In this paper, we show an implementation method of the box filter that requires less memory. Two types of wide-width but shallow memory are required in this method, but these memory can be efficiently realized on FPGA using distributed RAMs and block RAMs. In this method, the image is scanned in zigzag. The performance is decreased because of the necessity to overlap the zigzag scan, but it is fast enough for practical use. This zigzag scan enable to reduce the memory size to store data, but extra line buffers are required. Our approach is specially effective for applications that calculate cross-correlations for finding the best matching, because the overhead caused by the extra line buffers becomes relatively small in these applications. We show the effectiveness of our method using a stereo vision program based on the cost aggregation with guided filter.

关键词： field programmable gate arrays (FPGA)

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