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IEEE international Instrumentation and Measurement Technology conference (I2MTC)

作者： Bi, Tengfei Li, Xiaolu Chen, Wenbin Ma, Zichen Xu, Lijun Li, Duan Beihang Univ Sch Instrumentat & Optoelect Engn Beijing Peoples R China

ISBN: (纸本)9798350380903;9798350380910

Real-time ranging can boost the imaging performance and speed for full-waveform light detection and ranging (FW-LiDAR). To enhance ranging accuracy and maximum ranging rate, a two-parameter Gauss-Newton (Two-GN) based real-time ranging method is proposed for high-accuracy real-time ranging with lower hardware resource consumption. The Two-GN reduces the coefficient matrix size from 3x3 to 2x2 for obtaining quick iteration step vector solutions. FPGA implementation employs a module-level pipeline to enhance the maximum ranging rate. Experimental results showed that the ranging standard deviation (RStD) of Two-GN achieves 1.5 mm@51.90 dB, the absolute of mean ranging error (MRE) is lower than 2.0 mm@12.53 dB. The maximum ranging rate is improved to 2.21 MHz, the FPGA hardware resource and power consumption are reduced by over 30%. It is beneficial for real time imaging applications in autonomous driving and spacecraft space docking.

关键词： Full-waveform light detection and ranging field programmable gate array Gauss-Newton Two-parameter Gaussian ranging model

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SDA: Low-Bit Stable Diffusion Acceleration on Edge FPGAs

SDA: Low-Bit Stable Diffusion Acceleration on Edge FPGAs

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international conference on field programmable logic and applications

作者： Geng Yang Yanyue Xie Zhong Jia Xue Sung-En Chang Yanyu Li Peiyan Dong Jie Lei Weiying Xie Yanzhi Wang Xue Lin Zhenman Fang Xidian University Simon Fraser University Northeastern University University of Technology Sydney

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

This paper introduces SDA, the first effort to adapt the expensive stable diffusion (SD) model for edge FPGA deployment. First, we apply quantization-aware training to quantize its weights to 4 -bit and activations to 8 -bit ($W 4 A 8$) with a negligible accuracy loss. Based on that, we propose a high-performance hybrid systolic array (hybridSA) architecture that natively executes convolution and attention operators across varying quantization bit-widths (e.g., $W 4 A 8$ and all 8 -bit $Q K^{T} V$ in attention). To improve computational efficiency, hybridSA integrates diverse DSP packing techniques into hybrid weightstationary and output-stationary dataflows that are optimized for convolution and attention. It also supports flexible dataflow transitions to address the distinct demands of its output sequence by subsequent nonlinear operators. Moreover, we observe that nonlinear operators become the new performance bottleneck after the acceleration of convolution and attention, and offload them onto the FPGA as well. To reduce the latency of each nonlinear operator, we pipeline its own execution at a fine granularity. To minimize the resource utilization of nonlinear operators, we carefully balance their execution with hybridSA in a coarse-grained pipeline. Experimental results demonstrate that our low-bit ($W 4 A 8$) SDA accelerator on the embedded AMDXilinx ZCU102 FPGA achieves a speedup of $97.3 \times$ (which takes about $\mathrm{2 . 1}$ minutes for one SD inference), compared to the original SD-v1.5 model on the ARM Cortex-A53 CPU (which takes about 3.5 hours for one SD inference). Our SDA project is open sourced here: https://***/Michaela1224/SDA_code.

关键词： Training Quantization (signal) Convolution Pipelines Computer architecture Systolic arrays Computational efficiency Resource management logic field programmable gate arrays

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HASS: Hardware-Aware Sparsity Search for Dataflow DNN Accelerator

HASS: Hardware-Aware Sparsity Search for Dataflow DNN Accele...

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international conference on field programmable logic and applications

作者： Zhewen Yu Sudarshan Sreeram Krish Agrawal Junyi Wu Alexander Montgomerie-Corcoran Cheng Zhang Jianyi Cheng Christos-Savvas Bouganis Yiren Zhao Imperial College London UK University of Cambridge UK

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Deep Neural Networks (DNNs) excel in learning hierarchical representations from raw data, such as images, audio, and text. To compute these DNN models with high performance and energy efficiency, these models are usually deployed onto customized hardware accelerators. Among various accelerator designs, dataflow architecture has shown promising performance due to its layer-pipelined structure and its scalability in data *** weights and activations sparsity can further enhance memory storage and computation efficiency. However, existing approaches focus on exploiting sparsity in non-dataflow accelerators, which cannot be applied onto dataflow accelerators because of the large hardware design space introduced. As such, this could miss opportunities to find an optimal combination of sparsity features and hardware *** this paper, we propose a novel approach to exploit unstructured weights and activations sparsity for dataflow accelerators, using software and hardware co-optimization. We propose a Hardware-Aware Sparsity Search (HASS) to systematically determine an efficient sparsity solution for dataflow accelerators. Over a set of models, we achieve an efficiency improvement ranging from $1.3 \times$ to $4.2 \times$ compared to existing sparse designs, which are either non-dataflow or non-hardware-aware. Particularly, the throughput of MobileNetV3 can be optimized to 4895 images per second. HASS is open-source: https://***/Yu-Zhewen/HASS

关键词： Systematics Computational modeling Scalability Heuristic algorithms Memory management Artificial neural networks Throughput Software logic Optimization

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A Novel Method for Testing Digital ICs 3

A Novel Method for Testing Digital ICs

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3rd IEEE international conference on Industrial Electronics: Developments and applications, ICIDeA 2025

作者： Saw, Anjishnu Pradhan, Arjyadhara Dash, Nabakishor Rout, Minakhi Samal, Sarita School of Computer Science and Engineering KIIT Deemed to be University Bhubaneswar India School of Electrical Engineering KIIT Deemed to be University Bhubaneswar India

ISBN: (纸本)9798331533205

Digital logic is the foundation of circuits and are used almost everywhere. The most commonly found and used digital logic are manufactured and used in the form of 16 pin DIP Package. The magnitude of its usage in both common and sophisticated electronics necessitates the verification of these ICs for their proper functioning. However traditional IC testers are often bulky as well as expensive and is not a popular option among hobbyists and small-scale industries. A novel and simple method has been employed to check these ICs in the form of Cloud Database Integration to check these ICs. The development of such an IC tester has been discussed in detail, highlighting all the aspects. This paper also explores all the benefits that are associated with this low-cost IC tester including accessibility and ease of use. Overall, this research paper aims to contribute in the field of IC testing by providing an efficient and feasible solution © 2025 IEEE.

关键词： Integrated injection logic circuits

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Design and Implementation of Single Precision Floating-point Arithmetic logic Unit for RISC Processor on FPGA 3

Design and Implementation of Single Precision Floating-point...

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3rd IEEE international Maghreb Meeting of the conference on Sciences and Techniques of Automatic Control and Computer Engineering, MI-STA 2023

作者： Adela, Noor Alhuda Saad Yousuf, Amani Najeeb Ben Eljhani, Mohamed Muftah University of Tripoli Department of Computer Engineering Tripoli Libya

ISBN: (纸本)9798350319897

The main purpose of conducting this research is to design and implement a single precision floating-point arithmetic logic unit (ALU) that considered as a part of the math coprocessor. The main advantage of floating-point representation is that it can support more values than fixed-point and integer representations. Summation, Subtraction, multiplication and division are arithmetic functions in these calculations. In this floating-point unit, input must be provided in IEEE-754 format, which is 32 single precision floating point values. The application of This arithmetic unit is located in the math coprocessor. Commonly referred to as reduced instruction set computation (RISC) processor. In this processor, for a signal processing, a value with high accuracy is required and as it is an iterative process, the calculation should be as fast as possible. A fixed-point and integer central processing unit (CPU) can't meet the requirements. The floating-point representation can calculate very large or very small process quickly and accurately. The system designed, verified and implemented with Verilog hardware description language using Intel Altera software tools. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

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Goertzel Algorithm Design on field programmable Gate Arrays for Implementing Electric Power Measurement

Goertzel Algorithm Design on Field Programmable Gate Arrays ...

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2023 international conference on Computer Science, Information Technology and Engineering, ICCoSITE 2023

作者： Wibowo, Ferry Wahyu Wihayati Universitas Amikom Yogyakarta Department of Informatics Yogyakarta Indonesia Satya Wacana Christian University Doctoral Prog. of Computer Science Salatiga Indonesia

ISBN: (纸本)9798350320954

The Goertzel algorithm has a role in signaling to determine the modulus and phase of the harmonic components. This algorithm has the advantage of the Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT) algorithms in some cases of harmonics. Moreover, Goertzel's algorithm allows it to be used for signaling whose frequencies are not multiples of integers. This paper aims to design the hardware design of the Goertzel Algorithm by displaying register transfer logic (RTL), routing speed optimization, and component consumption of field programmable Gate Array (FPGA) resources. The FPGA type used in the design of this algorithm uses the SPARTAN-3E XC3S500E-4-FG320 evaluation board. The FPGA design from this algorithm is then applied to electric power measurement instrumentation. Hardware programming on this FPGA utilizes the Very High-Speed Integrated Circuit (VHSIC) Hardware Description Language, which is often referred to as VHDL. The results of consuming the components used in the FPGA for this design use 191 slices, 185 slice flip-flops, 356 of 4 inputs look-up table (LUT), 14 Input/Output (I/O), 14 Bonded I/O, 1 Multiplier MULT18X18SIO, and 1 Global Clock (GCLK). Meanwhile, the routing optimization speed of this FPGA model has a delay time of 7.693 ns or, in other words, it showed a maximum frequency of 129.988 MHz. © 2023 IEEE.

关键词： Electric power utilization

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Towards Securing Hard Real-Time Networked Embedded Devices and Systems: A cBPF Implementation for an FPGA 28

Towards Securing Hard Real-Time Networked Embedded Devices a...

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28th IEEE international conference on Emerging Technologies and Factory Automation, ETFA 2023

作者： Doran, Hans Dermot Schneider, Sven Leibundgut, Prosper Neuhaus, Stephan Eberli, Stefan Institute of Embedded Systems Zurich University of Applied Sciences Winterthur Switzerland Duagon AG Dietikon Switzerland

ISBN: (纸本)9798350339918

In this body of work we describe preliminary work implementing a Berkely Packet Filter, in its original conception, in an FPGA. The purpose is packet filtering and ingress traffic shaping in security-relevant applications in distributed embedded nodes. We specifically target PROFINET nodes in hard real-time applications where network security is an open issue. We describe the motivation, implementation and verification including performance characteristics. We conclude that such a filter can be used to not only for protection against simple denial-of-service attacks but also for ingress protocol management and potentially for the implementation of system-wide security policies. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

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A Smart System for Binary Image Denoising using DCNN on FPGA 6

A Smart System for Binary Image Denoising using DCNN on FPGA

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6th international conference on Inventive Computation Technologies, ICICT 2023

作者： Vignesh, O. Sivarajakrishnan, P. Sneha, V.S. Department of ECE Easwari Engineering College Chennai India

ISBN: (纸本)9798350398496

Integrated circuits based on digital image processing have been increasingly important in recent years due to their usefulness in many different fields, including manufacturing, agriculture, remote sensing, and medicine. The development of low-area, low-power, and low-delay processors is a significant challenge. The majority of these efforts have targeted efficient noise removal filtering by minimizing the resources required to accomplish it. Existing filtering approaches require a lot of space, a lot of power, and a lot of time since noise is dynamic and distributed randomly throughout images. Finally, this research work is extended by incorporating QCA technology to reduce the space, power, and time needed to build an efficient filtering method with altered noise deviation features. This research study proposes a majority logic gates technology to create DCNN-based FBF on a field-programmable gate array (FPGA). By using the vast majority of logic gates to design the MCSA, considerable gains can be achieved in terms of speed, execution time, area, power, and latency over the RCA used in traditional CNN. The proposed DCNN-FBF is also used in the implementation of an image denoising application. The proposed methodology has been shown to improve hardware performance relative to state-of-the-art methodologies, as evidenced by both hardware and extensive simulation findings. In addition, as compared to traditional filtering methods, the proposed image denoising solution has achieved higher values of structural similarity (SSIM) and PSNR. © 2023 IEEE.

关键词： logic gates

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Implementing Versatile programmable logic Functions Using Two Magnetization Switching Types in a Single Device (Adv. Funct. Mater. 3/2024)

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ADVANCED FUNCTIONAL MATERIALS 2024年第3期34卷 2308219-2308219页

作者： Huang, Xinhao Zhao, Yaru Wang, Xinran Wang, Fei Liu, Liang Yang, Hyunsoo Zhao, Weisheng Shi, Shuyuan Beihang Univ Fert Beijing Inst Sch Integrated Circuit Sci & Engn MIIT Key Lab Spintron Beijing 100191 Peoples R China Natl Univ Singapore Dept Elect & Comp Engn Singapore 117576 Singapore Shanghai Jiao Tong Univ Sch Phys & Astron Key Lab Artificial Struct & Quantum Control Minist Educ Shanghai 200240 Peoples R China

The efficient manipulation of magnetization using spin-orbit torques (SOTs) generated by heavy metals and topological insulators has attracted significant attention. However, the symmetry of these conventional materials makes it challenging to achieve deterministic switching of perpendicular magnetization by currents, which prevents the practical application of SOT-based spintronic devices such as magnetic memories and logics. Here, a composition gradient in a TaxTi1-x alloy is introduced and the field-free magnetization switching in TaxTi1-x/CoFeB heterostructures with controllable SOT efficiencies is realized. Additionally, by engineering the gradient with a tilting angle relative to the current injection arm of the device, highly asymmetric switching loops are achieved, which are attributed to tilted spin polarization. Based on these two switching types, namely field-free switching and field-assisted asymmetric switching, five programmable Boolean logic functions are successfully demonstrated using a single device. This work paves the way for high-density computing-in-memory applications with industry compatible artificially-designed asymmetric SOT materials.

关键词： alloy with composition gradient Boolean logic function computing-in-memory field-free switching spin-orbit torques

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The Road Less Traveled: Congestion-Aware NoC Placement and Packet Routing for FPGAs

The Road Less Traveled: Congestion-Aware NoC Placement and P...

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international conference on field programmable logic and applications

作者： Soheil Gholami Shahrouz Vaughn Betz Department of Electrical and Computer Engineering University of Toronto Toronto Canada

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

To help scale to ever-larger and more complex designs, recent FPGA architectures now integrate network-on-chips (NoCs). NoCs help transfer high-bandwidth data over long distances within the chip without using scarce low-delay long routing wire segments. While NoC-enhanced FPGAs aid system integration and design reuse, they also complicate FPGA computer-aided design (CAD) flows by introducing new constraints and metrics. Placement and routing needs to optimize NoC metrics like latency and bandwidth utilization and avoid link oversubscription (congestion), while simultaneously optimizing the programmable routing resource usage of the design modules attached to NoC routers. In this work we develop several new approaches to reduce NoC congestion while minimizing the impact on other design metrics. First, we incorporate a NoC link congestion cost into the placement engine of the open-source CAD flow, versatile place & route (VPR). Second, we integrate turn model NoC routing algorithms into the placement engine to leverage path diversity to further reduce congestion. On average over a suite of 29 benchmarks combining placement congestion modeling with turn model packet routing reduces NoC congestion by 90.7% at the cost of increasing aggregate bandwidth demand by 4%. In cases where the enhanced placement engine and NoC routing fail to fully resolve congestion, we formulate NoC routing as a boolean satisfiability (SAT) problem. This approach yields significant additional improvements; the combined algorithm reduces congestion by 95.1% compared to the baseline placement. Finally, we enhance the reinforcement learning (RL) agent in VPR’s placement engine by introducing a NoC-aware move type, resulting in an 8.8% reduction in wirelength on designs that make extensive use of the NoC.

关键词： Measurement Solid modeling Costs Design automation Aggregates Bandwidth Routing Wire field programmable gate arrays Engines

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