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检索条件"任意字段=International Conference on Field Programmable Logic and Applications"

共 16795 条记录，以下是4701-4710 订阅

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HeteroSim: A Heterogeneous CPU-FPGA Simulator 26

HeteroSim: A Heterogeneous CPU-FPGA Simulator

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26th international conference on field-programmable logic and applications (FPL)

作者： Feng, Liang Liang, Hao Sinha, Sharad Zhang, Wei Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Kowloon Hong Kong Peoples R China

ISBN: (纸本)9782839918442

Heterogeneous computing is rapidly gaining increased attention due to the promise it holds in overcoming power and performance walls in traditional computing systems. With its focus on customized processing nodes dedicated to the different tasks in an application, it is hoped that these walls will be overcome. Therefore, CPU-FPGA co-architectures are also gaining ground in application areas like recognition, mining, search, datacenter etc. However, research in CPU-FPGA co-architecture is constrained by the available synthesis and simulation tools which do not provide an integrated system level simulation and architectural exploration environment. This becomes critical when we incorporate novel memory hierarchies, multi-processor chip architectures, hardware level cache coherence etc. In this paper, we describe our open source and integrated system level simulator and architecture exploration tool called HeteroSim. It supports x86 based multi-core processor combined with a FPGA via bus-based architecture. It allows integrated system level simulation and returns performance metrics to understand application performance with respect to the simulated architectural configuration.

关键词： field programmable gate arrays (FPGA)

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applications of a Dual Function Multi-Port Converter Topology in DC Microgrid Systems 2

Applications of a Dual Function Multi-Port Converter Topolog...

引用

2nd IEEE international conference on Direct Current Microgrids (ICDCM)

作者： Muehlegg, Kyle Lehn, Peter W. Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 1A4 Canada

ISBN: (纸本)9781509044795

Climate change and Greenhouse Gas (GHG) emission reduction efforts have generated an interest in microgrid research due to its ability to integrate renewable energy sources and storage to existing grid infrastructure. Economizing microgrids through use of DC microgrids has become a major research focus. This paper proposes a novel converter topology that offers high-efficiency, reduced filter requirements and the ability to handle all DC/DC conversions within DC microgrid systems. Specifically, the paper investigates potential control schemes that integrate solar photovoltaic (PV) sources and energy storage technology to a DC microgrid system. Converter operation and control is verified using PSCADTM by simulating a realistic DC microgrid system using the proposed topology ti handle all DC/DC conversion. This paper examines system operating under normal operation (i.e. load demands, temperature and irradiance changes) and fault conditions.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Performance Analysis of Gate Engineered DGMOS-HFET using InP/InGaAs/InP Hetero structure and Effect of Misalignment on their Performance Parameters

Performance Analysis of Gate Engineered DGMOS-HFET using InP...

引用

international conference on Recent Innovations in Electrical, Electronics & Communication Engineering (ICRIEECE)

作者： Samparna Parida Soumya S Mohanty Monalisha Mishra Dept. of ECE ITER SOA University Bhubaneswar Odisha India

ISBN: (数字)9781538659953

ISBN: (纸本)9781538659960

In the current era of MOS Technology, DGMOS HFETs (Double Gate Metal Oxide Semiconductor Hetero structure field Effect Transistors) are one of the front runner in high speed switching applications. This paper presents the implementation of gate engineering in DGMOS HFET and effect of gate metal misalignment on their device parameters. An extensive simulation based study have been analysed on the back gate of the DGMOS HFET models by taking Drain Side Misalignment (DSM) and Source Side Misalignment (SSM). These models are Single Material Double Gate (SMDG) Double Material Double Gate (DMDG), Triple Material Double Gate (TMDG) structure. The parameters like surface potential, drain induced barrier lowering (DIBL), threshold voltage (V th ), subthreshold slope (SS), OFF current (I off ), ON current (I on ), transconductance (g m ), output conductance (g ds ), and I on /I off ratio have been analysed by using 2-Dimensional Sentaurus TCAD simulation.

关键词： logic gates HEMTs MODFETs Electric potential Metals Threshold voltage Ions

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Transparent FPGA Flow 26

Transparent FPGA Flow

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26th international conference on field-programmable logic and applications (FPL)

作者： Delporte, Baptiste Convers, Anthony Rigamonti, Roberto Dassatti, Alberto HEIG VD Sch Business & Engn Vaud HES SO REDS Inst CH-1400 Yverdon Switzerland

ISBN: (纸本)9782839918442

Heterogeneous computing has recently emerged as a way to circumvent the physical and technological limitations in the design of computing devices. The pressure exerted by the ever-growing demand of increased performances has eventually made the long-awaited dream of having a traditional CPU paired up with an FPGA a reality [1], [2]. FPGAs have proven indeed to be a viable solution for energy efficient high-performance computing [3], [4], [5]. However, while providing the system integrator a very compact and cost effective way to add advanced functionalities to products, this technological evolution has dramatically raised the overall complexity of the system: Exploiting the available capabilities now requires a wide range of competencies which are not always in the background of a company or institution. This requires a considerable effort at development time and often limits the applicability to a reduced set of supported brands/models, while being effective only when predicted usage patterns match the actual ones. High-Level Synthesis (HLS) [6] partially mitigates the above-mentioned problems by removing the language-barrier, but compiling and deploying a bitstream is an extremely long process, and again its development requires establishing a-priori usage patterns that might lead to a suboptimal usage of the available hardware. © 2016 EPFL.

关键词： field programmable gate arrays (FPGA)

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Performance Investigation of Gate-Engineered Recessed-S/D FDSOI MOSFETs for Low Power Analog/RF applications

Performance Investigation of Gate-Engineered Recessed-S/D FD...

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IEEE India conference (INDICON)

作者： Anjali Priya Nilesh Anand Srivastava Ram Awadh Mishra Department of Electronics and Communication Engineering Motilal Nehru National Institute of Technology Allahabad Prayagraj India

ISBN: (纸本)9781538682364

This paper explains the analog and RF performance of Gate-Engineered Recessed-Source/Drain (Re-S/D) Fully Depleted-Silicon on Insulator (FD-SOI) Metal Oxide Semiconductor field Effect Transistor (MOSFET). Re-S/D MOSFET has excellent capability of reducing series resistance which in turns improves the drive current capability and low leakages. In this paper, for the first time, the Analog and RF performance of Triple-Metal-Gate Re-S/D FD SOI MOSFET is analyzed to investigate the behavior of the device in Analog domain to be suggested for low power application. The device has been simulated using numerical 2-D device simulator from Silvaco ATLAS. The device performance has been evaluated with parameters such as drain current(I d ), transconductance(g m ), output conductance(g d ), device capacitance(C gs and C gd ), intrinsic gain(A v ), early voltage(V ea ), cut-off frequency(f T ), transconductance frequency product(TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP).

关键词： MOSFET logic gates Silicon-on-insulator Cutoff frequency Transconductance Radio frequency Performance evaluation

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Power Optimizations in MTJ-based Neural Networks through Stochastic Computing 22

Power Optimizations in MTJ-based Neural Networks through Sto...

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22nd IEEE/ACM international Symposium on Low Power Electronics and Design (ISLPED)

作者： Mondal, Ankit Srivastava, Ankur Univ Maryland Dept Elect & Comp Engn College Pk MD 20783 USA

ISBN: (纸本)9781509060238

Artificial Neural Networks (ANNs) have found widespread applications in tasks such as pattern recognition and image classification. However, hardware implementations of ANNs using conventional binary arithmetic units are computationally expensive, energy-intensive and have large area overheads. Stochastic Computing (SC) is an emerging paradigm which replaces these conventional units with simple logic circuits and is particularly suitable for fault-tolerant applications. Spintronic devices, such as Magnetic Tunnel Junctions (MTJs), are capable of replacing CMOS in memory and logic circuits. In this work, we propose an energy-efficient use of MTJs, which exhibit probabilistic switching behavior, as Stochastic Number Generators (SNGs), which forms the basis of our NN implementation in the SC domain. Further, error resilient target applications of NNs allow us to introduce Approximate Computing, a framework wherein accuracy of computations is traded-off for substantial reductions in power consumption. We propose approximating the synaptic weights in our MTJ-based NN implementation, in ways brought about by properties of our MTJ-SNG, to achieve energy-efficiency. We design an algorithm that can perform such approximations within a given error tolerance in a single-layer NN in an optimal way owing to the convexity of the problem formulation. We then use this algorithm and develop a heuristic approach for approximating multi-layer NNs. To give a perspective of the effectiveness of our approach, a 43% reduction in power consumption was obtained with less than 1% accuracy loss on a standard classification problem, with 26% being brought about by the proposed algorithm.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Evaluating Machine Learning Algorithms for applications with Humans in the Loop 14

Evaluating Machine Learning Algorithms for Applications with...

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14th IEEE international conference on Networking, Sensing and Control (ICNSC)

作者： Gopalakrishna, Aravind Kota Ozcelebi, Tanir Lukkien, Johan J. Liotta, Antonio Eindhoven Univ Technol Dept Math & Comp Sci Syst Architecture & Networking Grp Eindhoven Netherlands Eindhoven Univ Technol Dept Elect Engn Electroopt Commun Eindhoven Netherlands

ISBN: (纸本)9781509044290

applications employing data classification such as smart lighting that involve human factors such as perception lead to non-deterministic input-output relationships where more than one output may be acceptable for a given input. For these so called non-deterministic multiple output classification (nDMOC) problems, the relationship between the input and output may change over time making it difficult for the machine learning (ML) algorithms in a batch setting to make predictions for a given context. In this paper, we describe the nature of nDMOC problems and discuss the Relevance Score (RS) that is suitable in this context as a performance metric. RS determines the extent by which a predicted output is relevant to the user's context and behaviors, taking into account the inconsistencies that come with human (perception) factors. We tailor the RS metric so that it can be used to evaluate ML algorithms in an online setting at run-time. We assess the performance of a number of ML algorithms, using a smart lighting dataset with non-deterministic one-to-many input-output relationships. The results indicate that using RS instead of classification accuracy (CA) is suitable to analyze the performance of conventional ML algorithms applied to the category of nDMOC problems. Instance-based online ML gives the best RS performance. An interesting finding is that the RS keeps increasing with increasing number of samples, even after the CA performance converges.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Evaluation and Mitigation of Soft-Errors in Neural Network-based Object Detection in Three GPU Architectures 47

Evaluation and Mitigation of Soft-Errors in Neural Network-b...

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47th IEEE/IFIP Annual international conference on Dependable Systems and Networks (DSN)

作者： dos Santos, Fernando Fernandes Draghetti, Lucas Weigel, Lucas Carro, Luigi Navaux, Philippe Rech, Paolo Univ Fed Rio Grande do Sul Inst Informat Porto Alegre RS Brazil

ISBN: (纸本)9781538622728

In this paper, we evaluate the reliability of the You Only Look Once (YOLO) object detection framework. We have exposed to controlled neutron beams GPUs designed with three different architectures (Kepler, Maxwell, and Pascal) running Darknet, a Convolutional Neural Network for automotive applications, detecting objects in both Caltech and Visual Object Classes data sets. By analyzing the neural network corrupted output, we can distinguish between tolerable errors and critical errors, i.e., errors that could impact on real-time system execution. Additionally, we propose an Algorithm-Based Fault-Tolerance (ABFT) strategy to apply to the matrix multiplication kernels of neural networks able to detect and correct 50% to 60% of radiation-induced corruptions. We experimentally validate our hardening solution and compare its efficiency and efficacy with the available ECC.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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JetStream: An Open-Source High-Performance PCI Express 3 Streaming Library for FPGA-to-Host and FPGA-to-FPGA Communication 26

JetStream: An Open-Source High-Performance PCI Express 3 Str...

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26th international conference on field-programmable logic and applications (FPL)

作者： Vesper, Malte Koch, Dirk Vipin, Kizheppatt Fahmy, Suhaib A. Univ Manchester Sch Comp Sci Manchester M13 9PL Lancs England Mahindra Ecole Cent Hyderabad Andhra Pradesh India Univ Warwick Sch Engn Coventry CV4 7AL W Midlands England

ISBN: (纸本)9782839918442

Many FPGA-based accelerators are constrained by the available resources and multi-FPGA solutions can be necessary for building more capable systems. Available PCIe solutions provide only FPGA-to-Host communication. In this paper we present JetStream, an open-source1 modular PCIe 3 library, supporting not only fast FPGA-to-Host communication, but also allowing direct FPGA-to-FPGA communication which fully bypasses the memory subsystem. The direct mode saves memory bandwidth for multicast modes and permits to connect multiple FPGAs in various software defined topologies. We show the benefits of JetStream with a large FIR filter spanning four FPGA boards, achieving throughputs of up to 7.09 GB/s per link. Utilizing direct FPGA-to-FPGA transfers reduces the required memory bandwidth by up to 75%.

关键词： field programmable gate arrays (FPGA)

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A Rhythm Analysis-Based Model to Predict Sedentary Behaviors 17

A Rhythm Analysis-Based Model to Predict Sedentary Behaviors

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2nd IEEE/ACM international conference on Connected Health - applications, Systems and Engineering Technologies (CHASE)

作者： He, Qian Agu, Emmanuel O. Worcester Polytech Inst Dept Comp Sci Worcester MA 01609 USA

ISBN: (纸本)9781509047222

Sedentary behaviors such as sitting and watching TV are ubiquitous in modern societies. Increases in sedentary time have been linked with an increased risk of obesity, diabetes, cardiovascular disease, and all-cause mortality. While smart-phones and wearables can now detect sedentary user behaviors, few computational models exist for predicting when they will occur in future. In this paper, we propose a lightweight model to predict future sedentary behaviors, facilitating prevention rather than reactive interventions. Our models are based on the concept of rhythm analysis, an idea proposed by Lefebvre, which postulates that many human behaviors, the use of public spaces, and many phenomena all follow natural rhythms. Our work focuses on detecting the prevailing rhythms of sedentary behaviors and modeling the cyclical rhythm and linear rhythm in Lefebvre's philosophy using periodic functions (history-free) and linear functions (history-dependent) respectively. A person who lies on his couch at the same time every day is an example of a cyclical rhythm, while a person who lies down in exhaustion after vigorous exercise is an example of a linear rhythm. Our preliminary results from analyzing an existing dataset clearly show that rhythmical sedentary patterns do exist. Cyclical rhythms are more common than linear rhythms, and half-day rhythms, daily rhythms, weekly rhythms, and biweekly rhythms are clearly observed in a test dataset.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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