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检索条件"任意字段=International Conference on Field Programmable Logic and Applications"

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Tackling Gaps in Floating-Point Arithmetic: Unum Arithmetic Implementation on FPGA 19

Tackling Gaps in Floating-Point Arithmetic: Unum Arithmetic ...

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19th IEEE international conference on High Performance Computing and Communications (HPCC) / 15th IEEE international conference on Smart City (SmartCity) / 3rd IEEE international conference on Data Science and Systems (DSS)

作者： Hou, Junjie Zhu, Yongxin Shen, Yulan Li, Mengjun Wu, Han Song, Han Shanghai Jiao Tong Univ Sch Microelect Shanghai 200240 Peoples R China

ISBN: (纸本)9781538625880

Floating-point arithmetic is an important form in numerical computation, IEEE Standard for Floating-Point Arithmetic - IEEE 754 floats has been applied in overwhelming majority of microprocessors. However, as the increasing of data size and accuracy requirement of applications, bandwidth and precision are highly valued in floating-point computing, optimizing existing floating-point arithmetic is a way to improve current situation. Unum (universal number) arithmetic is a new floating-point arithmetic presented by John L. Gustafson in 2013, being compared with IEEE 754 floats, the outstanding features of unum are clearance of rounding errors, high information-per-bit and variable precision. However, unum was only implemented in software before due to technical complexity, we implement unum arithmetic on FPGA for the first time. We contrast the precision and bit width in computing with IEEE 754 floats, the comparison results show that unum need less bit width than IEEE 754 floats under same precision, it can decrease bandwidth requirement in computing.

关键词： Open area test sites conferences Adders field programmable gate arrays Bandwidth Hardware High performance computing

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Gesture-enabled Remote Control for Healthcare 17

Gesture-enabled Remote Control for Healthcare

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2nd IEEE/ACM international conference on Connected Health - applications, Systems and Engineering Technologies (CHASE)

作者： Zhao, Hongyang Wang, Shuangquan Zhou, Gang Zhang, Daqing Coll William & Mary Comp Sci Dept Williamsburg VA 23187 USA Telecom SudParis Inst Mines Telecom Evry France

ISBN: (纸本)9781509047222

In recent years, wearable sensor-based gesture recognition is proliferating in the field of healthcare. It could be used to enable remote control of medical devices, contactless navigation of X-ray display and Magnetic Resonance Imaging (MRI), and largely enhance patients' daily living capabilities. However, even though a few commercial or prototype devices are available for wearable gesture recognition, none of them provides a combination of (1) fully open API for various healthcare application development, (2) appropriate form factor for comfortable daily wear, and (3) affordable cost for large scale adoption. In addition, the existing gesture recognition algorithms are mainly designed for discrete gestures. Accurate recognition of continuous gestures is still a significant challenge, which prevents the wide usage of existing wearable gesture recognition technology. In this paper, we present Gemote, a smart wristband-based hardware/software platform for gesture recognition and remote control. Due to its affordability, small size, and comfortable profile, Gemote is an attractive option for mass consumption. Gemote provides full open API access for third party research and application development. In addition, it employs a novel continuous gesture segmentation and recognition algorithm, which accurately and automatically separates hand movements into segments, and merges adjacent segments if needed, so that each gesture only exists in one segment. Experiments with human subjects show that the recognition accuracy is 99.4% when users perform gestures discretely, and 94.6% when users perform gestures continuously.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Soft Computing applications Proceedings of the 7th international Workshop Soft Computing applications Sofa 2016

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2017年

作者： Valentina Emilia Balas Lakhmi C Jain Marius Mircea Balas

ISBN: (纸本)9783319625218;3319625217;9783319625249;3319625241;9783319625201

These two volumes constitute the Proceedings of the 7th international Workshop on Soft Computing applications (SOFA 2016), held on 2426 August 2016 in Arad, Romania. This edition was organized by Aurel Vlaicu University of Arad, Romania, University of Belgrade, Serbia, in conjunction with the Institute of Computer Science, Iasi Branch of the Romanian Academy, IEEE Romanian Section, Romanian Society of Control Engineering and Technical Informatics (SRAIT) - Arad Section, General Association of Engineers in Romania - Arad Section, and BTM Resources Arad. The soft computing concept was introduced by Lotfi Zadeh in 1991 and serves to highlight the emergence of computing methodologies in which the accent is on exploiting the tolerance for imprecision and uncertainty to achieve tractability, robustness and lower costs. Soft computing facilitates the combined use of fuzzy logic, neurocomputing, evolutionary computing and probabilistic computing, leading to the concept of hybrid intelligent systems. The rapid emergence of new tools and applications calls for a synergy of scientific and technological disciplines in order to reveal the great potential of soft computing in all domains. The conference papers included in these proceedings, published post-conference, were grouped into the following areas of research: Methods and applications in Electrical Engineering Knowledge-Based Technologies for Web applications, Cloud Computing, Security Algorithms and Computer Networks Biomedical applications Image, Text and Signal Processing Machine Learning and applications Business Process Management Fuzzy applications, Theory and Fuzzy Control Computational Intelligence in Education Soft Computing & Fuzzy logic in Biometrics (SCFLB) Soft Computing Algorithms Applied in Economy, Industry and Communication Technology Modelling and applications in Textiles The book helps to disseminate advances in selected active research directions in the field of soft computing, along with current issu

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CPU-FPGA Co-Optimization for Big Data applications: A Case Study of In-Memory Samtool Sorting 17

CPU-FPGA Co-Optimization for Big Data Applications: A Case S...

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ACM/SIGDA international Symposium on field-programmable Gate Arrays

作者： Cong, Jason Fang, Zhenman Huang, Muhuan Wang, Libo Wu, Di Univ Calif Los Angeles Los Angeles CA 90024 USA

ISBN: (纸本)9781450343541

To efficiently process a tremendous amount of data, today's big data applications tend to distribute the datasets into multiple partitions, such that each partition can be fit into memory and be processed by a separate core/server in parallel. Meanwhile, due to the limited scaling of general-purpose CPUs, FPGAs have emerged as an attractive alternative to accelerate big data applications due to their low power, high performance and energy efficiency. In this paper we aim to answer one key question: How should the multicore CPU and FPGA coordinate together to optimize the performance of big data applications? To address the above question, we conduct a step-by-step case study to perform CPU and FPGA co-optimization for in-memory Samtool sorting in genomic data processing, which is one of the most important big data applications for personalized healthcare. First, to accelerate the time-consuming compression algorithm and its associated cyclic redundancy check (CRC) in Samtool sorting, we implement a portable and maintainable FPGA accelerator using high-level synthesis (HLS). Although FPGAs are traditionally well-known to be suitable for compression and CRC, we find that a straightforward integration of this FPGA accelerator into the multi-threaded Samtool sorting only achieves marginal system throughput improvement over the software baseline running on a 12-core CPU. To improve system performance, we propose a dataflow execution model to effectively orchestrate the computation between the multi-threaded CPU and FPGA. Experimental results show that our co-optimized CPU-FPGA system achieves a 2.6x speedup for in-memory Samtool sorting.

关键词： Compression and CRC Genome data sorting Dataflow execution

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FPGA based Hand Sign Recognition System 2

FPGA based Hand Sign Recognition System

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2nd IEEE international conference on Recent Trends in Electronics, Information and Communication Technology (RTEICT)

作者： Mahesh, More Madhura Jerry, Moraes Savio Wadala, Dattatray Sujay Bade ARIET Elect & Telecommun Engn Thana Maharashtra India Vidyalankar Inst Technol Elect & Telecommun Engn Mumbai Maharashtra India

ISBN: (纸本)9781509037049

The prehistoric or primitive cave men's where communication first existed or started were using a means of sign language or gesture for communicating with each other. With the dawn of time, the man started working tirelessly to make his life better and better. The inventions of new technologies and the computer brought a huge change in the life of people. The Computer and advent of the internet made communication and transfer of information easier. But this is always an interaction with machines. The future era is conceiving of human-computer interaction (HCI) that can be used for implementing 3D applications in which user can move or rotate his hands without any input devices like keyboard or mouse. The communication involving hand gestures or signs for communication forms a basic platform for the proposed system. Many researchers have performed different work by using different algorithms. Some of them even have revised their previous algorithm. The current work and related literature review have given a way of developing a new system that can overcome all the system and should provide the best accuracy. The proposed system involves capture of images and then processing it, then filtering the unwanted part. The further processing of the image is carried out using FPGA, i.e. field programmable Gate Array. The system desires to give an excellent simulation, good accuracy, minimizes run time and efficiently reduces the power consumption. It will be forming a great alternative with low cost and best computational algorithm. The proposed system is desired to give better results and desired characteristics after implementation.

关键词： Human Computer Interaction (HCI) FPGA (field programmable Gate Array) Discrete Fourier transform (DFT) Radial Basis Function (RBF) Very Large Scale Integration (VLSI)

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A REAL-TIME FPGA IMPLEMENTATION OF VISIBLE/NEAR INFRARED FUSION BASED IMAGE ENHANCEMENT

A REAL-TIME FPGA IMPLEMENTATION OF VISIBLE/NEAR INFRARED FUS...

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IEEE international conference on Image Processing

作者： Mohamed Awad Ahmed Elliethy Hussein A. Aly Dept. of Computer Engineering Military Technical College Cairo Egypt

Near-infrared (NIR) band sensors capture achromatic images that contain complementary details of a scene which are diminished in visible (VS) band images when the scene is obscured by haze, mist, or fog. To exploit these complementary details, special cameras are produced that can capture both VS and NIR bands. Additionally, several sophisticated VS-NIR fusion approaches have been proposed to produce enhanced VS image with high quality. However, these approaches usually encounter heavy computations that are performed off cameras, limiting its suitableness for real-time applications. In this paper, we present an efficient design and FPGA implementation of VS-NIR fusion based image enhancement approach. To be suitable for camera hardware integration and to meet video real-time requirements, the proposed implementation is designed such that the consumed FPGA resources and the number of clock cycles required for producing the fused image are kept small. To achieve this, data and calculations are reused whenever possible in addition to the parallel and pipelined operations at both data and task levels. The proposed implementation is synthesized and validated on a low-end FPGA device. The proposed implementation produces a real time, indistinguishable, and 5 times faster fused image compared with optimized C++ implementation executed on a modern computer.

关键词： field programmable gate arrays Real-time systems Clocks Image enhancement Cameras Estimation Shift registers

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ContainerLeaks: Emerging Security Threats of Information Leakages in Container Clouds 47

ContainerLeaks: Emerging Security Threats of Information Lea...

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47th IEEE/IFIP Annual international conference on Dependable Systems and Networks (DSN)

作者： Gao, Xing Gu, Zhongshu Kayaalp, Mehmet Pendarakis, Dimitrios Wang, Haining Univ Delaware Newark DE 19716 USA Coll William & Mary Williamsburg VA 23185 USA IBM TJ Watson Res Ctr Yorktown Hts NY USA

ISBN: (纸本)9781538605424

Container technology provides a lightweight operating system level virtual hosting environment. Its emergence profoundly changes the development and deployment paradigms of multi-tier distributed applications. However, due to the incomplete implementation of system resource isolation mechanisms in the Linux kernel, some security concerns still exist for multiple containers sharing an operating system kernel on a multi-tenancy container cloud service. In this paper, we first present the information leakage channels we discovered that are accessible within the containers. Such channels expose a spectrum of system-wide host information to the containers without proper resource partitioning. By exploiting such leaked host information, it becomes much easier for malicious adversaries (acting as tenants in the container clouds) to launch advanced attacks that might impact the reliability of cloud services. Additionally, we discuss the root causes of the containers' information leakages and propose a two-stage defense approach. As demonstrated in the evaluation, our solution is effective and incurs trivial performance overhead.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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RSVP: Soft Error Resilient Power Savings at Near-Threshold Voltage using Register Vulnerability 47

RSVP: Soft Error Resilient Power Savings at Near-Threshold V...

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47th IEEE/IFIP Annual international conference on Dependable Systems and Networks (DSN)

作者： Tan, Li DeBardeleben, Nathan Guan, Qiang Blanchard, Sean Lang, Michael Los Alamos Natl Lab Ultrascale Syst Res Ctr Los Alamos NM 87545 USA

ISBN: (纸本)9781538622728

With the ever-growing scaling of computing capability, computing systems like supercomputers and embedded systems are bounded by limited power nowadays. Upon the mutually constrained nature between power efficiency and resilience, trade-offs of them have been extensively studied for achieving the optimal performance-power ratio, either under a certain power cap, or within the requirement of quality metrics of applications. Theoretically, running programs in the low-power mode of computational components (e.g., CPU/GPU) can lead to increasing on-chip failure rates in terms of register-level susceptibility to soft errors. However, experimentally, such errors may not arise due to register vulnerability - errors occur at non-vulnerable register access intervals are invalidated and thus will not propagate to later execution. In this work, leveraging register vulnerability, we investigate the validity of failure rates in computing systems at Near-Threshold Voltage (NTV), and empirically evaluate the practice of achieving optimal power savings without incurring observable number of soft errors during program runs. We propose the framework of RegiSter Vulnerability based Power efficiency (RSVP) for reliable and power efficient computing. Experimental results for a wide spectrum of applications on a power-aware simulated platform demonstrate the power saving capability of RSVP, by 11.2% on average, without incurring runtime soft errors at the optimal NTV level for power savings.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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FPGA implementation of adaptive beamforming in hearing aids 39

FPGA implementation of adaptive beamforming in hearing aids

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39th Annual international conference of the IEEE Engineering in Medicine and Biology Society, EMBC 2017

作者： Samtani, Kartik Thomas, Jobin Varma, G. Abhinav Sumam David, S. Deepu, S.P. Department of Electronics and Communication Engineering National Institute of Technology Karnataka Surathkal Mangalore575025 India

ISBN: (纸本)9781509028092

Beamforming is a spatial filtering technique used in hearing aids to improve target sound reception by reducing interference from other directions. In this paper we propose improvements in an existing architecture present for two omnidirectional microphone array based adaptive beamforming for hearing aid applications and implement the same on Xilinx Artix 7 FPGA using VHDL coding and Xilinx Vivador 2015.2. The nulls are introduced in particular directions by combination of two fixed polar patterns. This combination can be adaptively controlled to steer the null in the direction of noise. The beamform patterns and improvements in SNR values obtained from experiments in a conference room environment are analyzed. © 2017 IEEE.

关键词： Microphones Gain Array signal processing Hardware field programmable gate arrays Hearing aids Speech

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The Next Generation Platform as a Service Cloudifying Service Deployments in Telco-Operators Infrastructure

The Next Generation Platform as a Service Cloudifying Servic...

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international conference on Telecommunications (ICT)

作者： A. Mimidis E. Ollora J. Soler S. Bessem L. Roullet S. Van Rossem S. Pinneterre M. Paolino D. Raho X. Du J. Chesterfield M. Flouris L. Mariani O. Riganelli M. Mobilio A. Ramos I. Labrador A. Broadbent P. Veitch M. Zembra DTU Fotonik Lyngby Denmark Nokia-Bell Labs Paris France Ghent University - imec Ghent Belgium Virtual Open Systems Grenoble France OnApp London United Kingdom University of Milano-Bicocca Milano Italy ATOS Madrid Spain British Telecom London UnitedKingdom Vertical M2M París France

5G standard emerges at a particular time in technology history when cloud transforms deeply almost all industries and services: it becomes obvious that innovations have to be made cloud-native for being successful. 5G must become the ubiquitous fabric blending universal connectivity (to humans, robots, sensors...) with cloud versatility and scalability. For realizing this vision, another model than laaS must be adopted, the Platform as a Service (PaaS), which should be built to support telco-grade requirements and combine all sort of third-party applications. These are the core objectives of the Next Generation Platform as a Service (NGPaaS) project, a H2020 5G PPP Phase 2 project. The paper presents the project fundamentals, its architectural proposal and most relevant features.

关键词： 5G mobile communication Monitoring field programmable gate arrays Business Virtualization Platform as a service

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