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检索条件"任意字段=International Conference on Field Programmable Logic and Applications"

共 16795 条记录，以下是4721-4730 订阅

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Multi-Bit Digital Receiver Design For Radar Signature Estimation

Multi-Bit Digital Receiver Design For Radar Signature Estima...

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IEEE international conference on Recent Trends in Electronics, Information & Communication Technology

作者： Deeksha Gupta A. A. Bazil Raj Abhijit Kulkarni Dept. of Electronics Engineering Defence Institute of Advanced Technology Defence Avionic Research Establishment DARE

ISBN: (数字)9781538624401

ISBN: (纸本)9781538624418

This paper brings out a unique FPGA based pulse detection and characterization approach for digital wideband ESM receiver targeted for EW applications. The proposed approach uses a high speed ADC and FPGA based architecture for sampling and digital signal processing of the received RADAR signals to extract the key parameters such as Frequency (F), Time of Arrival (TOA), Pulse Width (PW) and Pulse Repetition Interval (PRI). The proposed novel FFT based digital EW receiver is designed and verified by MATLAB and SIMULINK tools and VHDL code for same algorithm is generated using HDL Coder for FPGA implementation. The current paper uses 512-point FFT based digital EW receiver, requires minimum pulse width of 750 ns and frequency separation between two simultaneous pulses is 2.63 MHz to extract the key parameters accurately. The simulated and measured results for Pulse detection algorithm are presented.

关键词： EW ESM Digital receiver LPI POI ADC FFT Peak detection Intermediate frequency (IF) HDL coder FPGA VHDL Pulse description words (PDW) Digital receiver field programmable gate arrays electronic warfare peak detection very high density lipoproteins Fast Fourier transform LPI LYSINURIC PROTEIN INTOLERANCE POIs European Stability Mechanism PULSE WIDTH analog digital converter

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Harnessing programmable SoCs to Develop Cost-effective Network Quality Monitoring Devices 26

Harnessing Programmable SoCs to Develop Cost-effective Netwo...

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26th international conference on field-programmable logic and applications (FPL)

作者： Ruiz, M. Ramos, J. Sutter, G. Lopez-Buedo, S. Lopez de Vergara, J. E. Sisterna, C. Univ Autonoma Madrid High Performance Comp & Networking Res Grp E-28049 Madrid Spain NAUDIT HPCN Madrid Spain Univ Nacl San Juan Inst Invest Antisism San Juan Argentina

ISBN: (纸本)9782839918442

Networks are currently essential for computing: It is therefore essential to guarantee the quality of network links in order to ensure a proper operation of computing systems. However, a widespread deployment of network monitoring devices might not be economically feasible. In this paper, we propose the use of programmable System-on-Chip FPGAs (PSoCs) for enabling a comprehensive testing of networks. Software-only solutions are no longer valid, because the timescales of current networks call for custom-hardware solutions. Thus, we show that PSoCs are a perfect fit for network quality monitoring devices, by mapping the required measurements to the capabilities of such devices. In order to demonstrate the benefits of PSoCs to monitor the quality of network links, we have developed a prototype based on Xilinx Zynq that is capable of measuring the key performance indicators of Gigabit Ethernet networks, namely: available bandwidth, packet loss, delay and jitter. The monitoring probe features GPS-based timestamping, thus enabling the construction of network delay maps. We present the benefits of the proposed approach in terms of cost and simplicity, and we also show how it could be expanded to multi-Gb/s networks.

关键词： Cost effectiveness

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Efficient and Reliable High-Level Synthesis Design Space Explorer for FPGAs 26

Efficient and Reliable High-Level Synthesis Design Space Exp...

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26th international conference on field-programmable logic and applications (FPL)

作者： Liu, Dong Schafer, Benjamin Carrion Hong Kong Polytech Univ Dept Elect & Informat Engn Hong Kong Hong Kong Peoples R China

ISBN: (纸本)9782839918442

This paper presents a dedicated High-Level Synthesis (HLS) Design Space Explorer (DSE) for FPGAs. C-based VLSI design has the advantage over conventional RTL design that it allows the generation of micro-architectures with unique area vs. performance trade-offs without having to modify the original behavioral description (in this work area vs. latency). This is typically done by modifying the Functional Unit (FU) constraint file or setting different synthesis directives e.g. unroll loops or synthesize arrays as RAM or registers. The result of the design space exploration is a set of Pareto-optimal designs. In this work, we first investigate the quality of the exploration results when using the results reported after HLS (in particular the area) to guide the explorer in finding Pareto-optimal designs. We found that due to the nature of how HLS tools pre-characterize, the area and delay of basic logic primitives and the FPGAs internal structure the area results are not accurate and hence making it necessary to perform a logic synthesis after each newly generated design. This in turn leads to unacceptable long running time. This work therefore presents a dedicated DSE for FPGAs based on a pruning with adaptive windowing method to extract the design candidates to be further (logic) synthesized after HLS. The adaptive windowing is based on a learning method inspired from Rival Penalized Competitive Learning (RPCL) model in order to classify which designs need to be synthesized to find the true Pareto-optimal designs. Results show that our method leads to similar results compared to an explorer which performs a logic synthesis for each newly generated design, while being much faster.

关键词： field programmable gate arrays (FPGA)

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Runtime-Quality Tradeoff in Partitioning Based Multithreaded Packing 26

Runtime-Quality Tradeoff in Partitioning Based Multithreaded...

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26th international conference on field-programmable logic and applications (FPL)

作者： Vercruyce, Dries Vansteenkiste, Elias Stroobandt, Dirk Univ Ghent ELIS Dept Comp Syst Lab Ghent Belgium

ISBN: (纸本)9782839918442

It takes a long time to generate a configuration for an FPGA starting from a description of a digital circuit in a hardware design language. This configuration should have a high quality so that the FPGA resources are used in an efficient way with the maximum clock frequency and minimizing the power consumption. In this work we present two new packing algorithms that obtain better quality and faster runtimes when compared to the frequently used AAPack packer. The partitioning based methodology allows us to exploit the advantage of multi-threading on commodity hardware. Firstly we demonstrate the benefits of our fully partitioning based PartSA packer. Existing packers with a partitioning based approach have problems with the cluster size and bandwidth constraint of the functional blocks. We added a fast simulated annealing step after partitioning to solve these problems. A gain of 26% in total wirelength is obtained while reaching up to 2.3x faster packing runtimes for large circuits on a CPU with four cores. Unfortunately the PartSA packer can not be used for architectures without a complete crossbar in the functional blocks. Therefore a second packer is proposed that combines the benefits of partitioning based and seed based packing. MultiPart has up to 4x faster packing runtimes while still having a gain of 20% in total wirelength.

关键词： field programmable gate arrays (FPGA)

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TeSHoP : A Temperature Sensing based Hotspot-Driven Placement Technique for FPGAs 26

TeSHoP : A Temperature Sensing based Hotspot-Driven Placemen...

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26th international conference on field-programmable logic and applications (FPL)

作者： Lu, Weina Hu, Yu Ye, Jing Li, Xiaowei Chinese Acad Sci Inst Comp Technol State Key Lab Comp Architecture Beijing 100864 Peoples R China Chinese Acad Sci Grad Univ Beijing 100864 Peoples R China

ISBN: (纸本)9782839918442

The rapid shrinking of the feature size in CMOS technology has significantly increased the power density of integrated circuits, leading to excessive temperature. Though online thermal management techniques such as DVFS and task migration can mitigate the temperature issue, but usually incur significant performance penalty. Therefore, it is crucial to optimize temperature at the design stage. In this work, we propose the TeSHoP, a Temperature Sensing based Hotspot-Driven Placement technique for FPGAs. Firstly, the un-optimized circuit along with a sensor network is run in FPGA to obtain the real temperature profile of the circuit. Then, based on the temperature profile, we proceed a one-off adjustment of the circuit placement for hotspot optimization. The optimization is modeled as a Hyper Minimum Bipartite Matching problem for solving. We implement the whole optimization flow in a real FPGA, with extension of the VTR-to-Bitstream tool. Experimental results on Xilinx Virtex-6 FPGA show that the reduction of peak temperature and the improvement of thermal uniformity can be up to 7.5 degrees C and 13.9% respectively.

关键词： field programmable gate arrays (FPGA)

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Automated Extra Pipeline Analysis of applications mapped to Xilinx UltraScale plus FPGAs 26

Automated Extra Pipeline Analysis of Applications mapped to ...

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26th international conference on field-programmable logic and applications (FPL)

作者： Ganusov, Ilya Fraisse, Henri Ng, Aaron Possignolo, Rafael Trapani Das, Sabya Xilinx Inc 2100 Log Dr San Jose CA 95124 USA Univ Calif Santa Cruz Dept Comp Engn Santa Cruz CA 95064 USA

ISBN: (纸本)9782839918442

This paper describes the methodology and algorithms behind extra pipeline analysis tools released in the Xilinx Vivado Design Suite version 2015.3. Extra pipelining is one of the most effective ways to improve performance of FPGA applications. Manual pipelining, however, often requires significant efforts from FPGA designers who need to explore various changes in the RTL and re-run the flow iteratively. The automatic pipelining approach described in this paper, in contrast, allows FPGA users to explore latency vs. performance trade-offs of their designs before investing time and effort into modifying RTL. We describe algorithms behind these tools which use simple cut heuristics to maximize performance improvement while minimizing additional latency and register overhead. To demonstrate the effectiveness of the proposed approach, we analyse a set of 93 commercial FPGA applications and IP blocks mapped to Xilinx UltraScale+ and UltraScale generations of FPGAs. The results show that extra pipelining can provide from 18% to 29% potential Fmax improvement on average. It also shows that the distribution of improvements is bimodal, with almost half of benchmark suite designs showing no improvement due to the presence of large loops. Finally, we demonstrate that highly-pipelined designs map well to UltraScale+ and UltraScale FPGA architectures. Our approach demonstrates 19% and 20% Fmax improvement potential for the UltraScale+ and UltraScale architectures respectively, with the majority of applications reaching their loop limit through pipelining.

关键词： field programmable gate arrays (FPGA)

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Annotation-Based Finite-State Transducers on Reconfigurable Devices 26

Annotation-Based Finite-State Transducers on Reconfigurable ...

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26th international conference on field-programmable logic and applications (FPL)

作者： Polig, Raphael Atasu, Kubilay Hagleitner, Christoph Xu, Theresa Nakayama, Akihiro IBM Res Zurich Ruschlikon Switzerland IBM Syst Toronto ON Canada IBM Watson Tokyo Japan

ISBN: (纸本)9782839918442

With the ever growing amount of unstructured data, high-speed content analysis becomes ever more important. Enabling efficient search functions to help locate specific and relevant information hidden in this big data is a crucial task of today's enterprise systems, and can lead to valuable insights. A key component of content analysis systems are text parsers, which transform unstructured text data into structured information. Cascaded grammars offer a popular and powerful representation of text parsers by enabling the definition of more complex patterns in terms of simpler ones in a hierarchical fashion. This work presents a compilation framework to generate an optimized FPGA pipeline from a cascaded grammar description. We also describe the system integration and the way FPGA-based accelerators can be used as part of larger analysis tasks within Unstructured Information Management Application (UIMA) pipelines. We compare the performance of the hardware-accelerated system and a commercial software implementation using real-life UIMA pipelines from the healthcare domain. We show that the FPGA-accelerated system processes the parsing stage of a UIMA pipeline up to 31 times faster than the software implementation running on a high-end server, which results in an acceleration of up to 5 times for the complete pipeline.

关键词： field programmable gate arrays (FPGA)

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Haptics and Virtual Reality Based Bilateral Telemanipulation of Miniature Aerial Vehicle Over Open Communication Network 18

Haptics and Virtual Reality Based Bilateral Telemanipulation...

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18th international conference on Advanced Robotics (ICAR)

作者： Islam, Shafiqul Gan, Dongming Ashour, Reem Dario, Paolo Dias, Jorge Seneviratne, Lakmal D. Khalifa Univ Sci & Technol Abu Dhabi 1027788 U Arab Emirates Univ Ottawa Ottawa ON K1N 6N5 Canada SSSA Biomed Engn & BioRobot Inst Pisa Italy Univ Coimbra Coimbra Portugal Kings Coll London London England

ISBN: (纸本)9781538631577

In this paper, we develop haptic interface system for bilateral telemanipulation of unmanned miniature aerial vehicle (MAV). The proposed interface allows operator to navigate MAV in order to control and interact with uncertain indoor flying environments without using vision systems. The master interface combines bilateral shared control terms with the reflected remote interaction force fields mapped by two different types of force field algorithms as potential force field and spring-damper force field. The shared control strategy for the master comprises velocity signals of the remote MAV with the scaled position of the master haptic manipulator. The bilateral shared input interface for the slave is designed by combining scaled position of the master manipulator with the velocity of the remote MAV. The data transmission between ground station and remote vehicle are carried out by open internet communication network. In contrast with other haptic interface system, the proposed interface system only uses laser technology equipped with the slave MAV. Compared with potential force field based interface, the interface introduced in this paper provides better situational awareness about remote environment helping operator to navigate and control MAV for safe interaction with uncertain indoor dynamic environment. Experimental results together with comparative studies on laboratory made quadrotor MAV are presented to demonstrate the effectiveness of the proposed methods for real-time applications.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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DT-CGRA: Dual-Track Coarse-Grained Reconfigurable Architecture for Stream applications 26

DT-CGRA: Dual-Track Coarse-Grained Reconfigurable Architectu...

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26th international conference on field-programmable logic and applications (FPL)

作者： Fan, Xitian Li, Huimin Cao, Wei Wang, Lingli Fudan Univ State Key Lab ASIC & Syst 825 Zhangheng Rd Shanghai 201203 Peoples R China

ISBN: (纸本)9782839918442

This paper presents a new type of coarse-grained reconfigurable architecture (CGRA) for the object inference domain in machine learning. The proposed CGRA is optimized for stream processing and a correspondent programming model called dual-track model is proposed. The CGRA is realized in Verilog HDL and implemented in SMIC 55 nm process, with the footprint of 3.79 mm(2) and consuming 1.79 W at 500 MHz. To evaluate the performance, eight machine-learning algorithms including HOG, CNN, k-means, PCA, SPM, linear-SVM, Softmax and Joint-Bayesian are selected as benchmarks. These algorithms cover a general machine learning flow in object inference domain: feature extraction, feature selection and inference. The experimental results show that the proposed CGRA can gain 1443x average energy efficiency comparing to the Intel i7-3770 CPU and 7.82x energy efficiency comparing to a high performance FPGA solution [19].

关键词： coarse-grained reconfigurable architecture domain-specific computing machine learning object inference

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Control Flow for Robust One-Shot Robot Programming using Entity-based Resources 18

Control Flow for Robust One-Shot Robot Programming using Ent...

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18th international conference on Advanced Robotics (ICAR)

作者： Orendt, Eric M. Henrich, Dominik Univ Bayreuth Chair Appl Comp Sci 3 Robot & Embedded Syst D-95445 Bayreuth Germany

ISBN: (纸本)9781538631577

Robotic systems are used in a wide range of applications. With an intuitive programming system from previous work we are able to transfer the advantages of robotic systems into more unstructured environments like private households or small and medium sized enterprises. An important challenge in this field is to enable non-experts to use all the capabilities of a robot. This includes two aspects: Robots must be intuitive to program and robust to execute. Our recently presented One-Shot programming framework concerns both aspects. The main contribution of this work is to extend the existing framework and to raise the usability of our approach. With this motivation we identify generalization chances in our task representation model and introduce an extension of our programming paradigm by integrating control flow to increase its capabilities. The proposed system concept enables users to guide a robot kinesthetically through a task without prior knowledge. By observing resources in the workspace, the demonstrated task is encoded as a finite state machine (FSM). This FSM allows the reproduction of a task by the robot itself and also offers two ways to control the flow of a robot program: Loops and Branches. With these statements a non-expert user gains the opportunity to program even more complex task solutions.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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