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检索条件"任意字段=International Conference on Field Programmable Logic and Applications"

共 16770 条记录，以下是4761-4770 订阅

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Mixed radix CORDIC FFT algorithm for OFDM WPAN applications

Mixed radix CORDIC FFT algorithm for OFDM WPAN applications

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2017 international conference on Energy, Communication, Data Analytics and Soft Computing, ICECDS 2017

作者： Borole, Yogini Dilip Dethe, C.G. Electronics and Telecommunication National Institute of Electronics and Information Technology Aurangabad India

ISBN: (纸本)9781538618868

This electronic record portrays the technique for usage of Fast Fourier transform for wireless communication systems, like OFDM, digital video broadcasting, digital audio broadcasting, and worldwide inter-operability for microwave access. The high speed and low area FFT algorithm using CORDIC and radix 2 5 calculation is proposed here. CORDIC is fundamentally DSP application yet here it is utilized for twiddle component augmentation. Radix 2 5 fft calculation is utilized for lessening of complex duplication. The proposed computation minimizes the amount of multipliers. Plot outlines show that the FFT arranged by the proposed framework shows a lower hardware with more quality than existing systems. Our designed has a working frequency up to 420.203 MHZ. CORDIC computation is executed in both MATLAB and in Xilinx on Virtex-5. © 2017 IEEE.

关键词： field programmable gate arrays (FPGA)

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ESP: A Machine Learning Approach to Predicting Application Interference 14

ESP: A Machine Learning Approach to Predicting Application I...

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14th IEEE international conference on Autonomic Computing (ICAC)

作者： Mishra, Nikita Lafferty, John D. Hoffmann, Henry Univ Chicago Dept Comp Sci Chicago IL 60637 USA Univ Chicago Dept Stat Chicago IL 60637 USA

ISBN: (纸本)9781538617625

Independent applications co-scheduled on the same hardware will interfere with one another, affecting performance in complicated ways. Predicting this interference is key to efficiently scheduling applications on shared hardware, but forming accurate predictions is difficult because there are many shared hardware features that could lead to the interference. In this paper we investigate machine learning approaches (specifically, regularization) to understand the relation between those hardware features and application interference. We propose ESP, a highly accurate and fast regularization technique for application interference prediction. To demonstrate this practicality, we implement ESP and integrate it into a scheduler for both single and multi-node Linux/x86 systems and compare the scheduling performance to state-of-the-art heuristics. We find that ESP-based schedulers increase throughput by 1.25-1.8x depending on the scheduling scenario. Additionally, we find that ESP's accurate predictions allow schedulers to avoid catastrophic decisions, which heuristic approaches fundamentally cannot detect.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Towards Efficient Design Space Exploration of FPGA-based Accelerators for Streaming HPC applications 17

Towards Efficient Design Space Exploration of FPGA-based Acc...

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ACM/SIGDA international Symposium on field-programmable Gate Arrays

作者： Koraei, Mostafa Jahre, Magnus Fatemi, S. Omid Univ Tehran Tehran Iran NTNU Trondheim Trondheim Norway

ISBN: (纸本)9781450343541

Streaming HPC applications are data intensive and have widespread use in various fields (e.g., Computational Fluid Dynamics and Bioinformatics). These applications consist of different processing kernels where each kernel performs a specific computation on its input data. The objective of the optimization process is to maximize performance. FPGAs show great promise for accelerating streaming applications because of their low power consumption combined with high theoretical compute capabilities. However, mapping an HPC application to a reconfigurable fabric is a challenging task. The challenge is exacerbated by need to temporally partition computational kernels when application requirements exceed resource availability. In this poster, we present work towards a novel design methodology for exploring design space of streaming HPC applications on FPGAs. We assume that the designer can represent the target application with a Synchronous Data Flow Graph (SDFG). In the SDFG, the nodes are compute kernels and the edges signify data flow between kernels. The designer should also determine the problem size of the application and the volume of raw data on each memory source of the SDFG. The output of our method is a set of FPGA configurations that each contain one or more SDFG nodes. The methodology consists of three main steps. In Step 1, we enumerate the valid partitions and the base configurations. In Step 2, we find the feasible base configurations given the hardware resources available and a library of processing kernel implementations. Finally, we use a performance model to calculate the execution time of each partition in Step 3. Our current assumption is that it is advantageous to represent SDFG at a coarse granularity since this enables exhaustive exploration of the design space for practical applications. This approach has yielded promising preliminary results. In one case, the temporal configuration selected by our methodology outperformed the direct mapping by 3X.

关键词： Reconfigurable Computing FPGA HPC SDFG Acceleration Application mapping

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New Results on Pre-aggregation Functions: introducing (light) pre-t-norms 17

New Results on Pre-aggregation Functions: introducing (light...

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Joint 17th World Congress of international-Fuzzy-Systems-Association / 9th international conference on Soft Computing and Intelligent Systems (IFSA-SCIS)

作者： Dimuro, Gracaliz P. Bustince, Humberto Fernandez, Javier Mesiar, Radko Bedregal, Benjamin UPNA ISC Pamplona Spain Fundacao Univ Fed Rio Grande C3 Rio Grande RS Brazil UPNA ISC DAC Pamplona Spain Slovak Univ Technol Bratislava DM Bratislava Slovakia Univ Fed Rio Grande do Norte DIMAP Natal RN Brazil

ISBN: (纸本)9781509049172

The aim of this paper is to enlarge the knowledge about the promising concept of a pre-aggregation function introduced by Lucca et al., which is a kind of "aggregation" concept that no longer requires monotonicity in all the function domain. For that, we introduce the notion of pre-t-norm, based on the important concept of t-norm. We also study the case of the so-called light pre-t-norms, which are particular non necessarily associative, commutative functions with neutral element e = 1, allowing for applications that do not require the associativity property, as it was extensively discussed in the literature. We analyse some properties of (light) pre-t-norms and the classes of (light) pre-t-norms, providing several examples.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Principal Component Analysis Approach in Selecting Type-1 and Type-2 Fuzzy Membership Functions for High-dimensional Data 17

Principal Component Analysis Approach in Selecting Type-1 an...

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Joint 17th World Congress of international-Fuzzy-Systems-Association / 9th international conference on Soft Computing and Intelligent Systems (IFSA-SCIS)

作者： Raj, Desh Gupta, Aditya Tanna, Kenil Garg, Bhuvnesh Rhee, Frank Chung-Hoon Indian Inst Technol Guwahati Dept Comp Sci & Engn Gauhati 781039 India Indian Inst Technol Guwahati Dept Math Gauhati 781039 India Hanyang Univ Dept Elect & Commun Engn Ansan 15588 South Korea

ISBN: (纸本)9781509049172

With increased interest in learning from data, algorithms that manipulate datasets containing hundreds of features have become popular in various fields such as medicine, image processing, geolocation, biochemistry, and computational linguistics. Since a number of these applications exploit the power of fuzzy sets in representing uncertainties, it may be considered essential to describe a method for selecting the most suitable fuzzy membership function to represent a high-dimensional dataset. In this paper, we propose such a method, which is based on dimensionality reduction using the Principal Component Analysis (PCA) technique, followed by the Wilcoxon Minimal Bin Size algorithm, which has earlier been evaluated on multidimensional datasets up to 8 dimensions. We further demonstrate our proposed method using two real datasets consisting of 281 and 500 features, respectively.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Highly-Available applications on Unreliable Infrastructure: Microservice Architectures in Practice

Highly-Available Applications on Unreliable Infrastructure: ...

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IEEE international conference on Software Quality, Reliability and Security (Companion Volume)

作者： Richter, Daniel Konrad, Marcus Utecht, Katharina Polze, Andreas Univ Potsdam Hasso Plattner Inst POB 90 04 60 D-14440 Potsdam Germany DB Systel GmbH Caroline Michaelis Str 5-11 D-10115 Berlin Germany

ISBN: (纸本)9781538620724

In contrast to applications relying on specialized and expensive highly-available infrastructure, the basic approach of microservice architectures to achieve fault tolerance - and finally high availability - is to modularize the software system into small, self-contained services that are connected via implementation-independent interfaces. Microservices and all dependencies are deployed into self-contained environments called containers that are executed as multiple redundant instances. If a service fails, other instances will often still work and take over. Due to the possibility of failing infrastructure, these services have to be deployed on several physical systems. This horizontal scaling of redundant service instances can also be used for load-balancing. Decoupling the service communication using asynchronous message queues can increase fault tolerance, too. The Deutsche Bahn AG (German railway company) uses as system called EPA for seat reservations for inter-urban rail services. Despite its high availability, the EPA system in its current state has several disadvantages such as high operational cost, need for special hardware, technological dependencies, and expensive and time-consuming updates. With the help of a prototype, we evaluate the general properties of a microservice architecture and its dependability with reference to the legacy system. We focus on requirements for an equivalent microservice-based system and the migration process;services and data, containerization, communication via message queues;and achieving similar fault tolerance and high availability with the help of replication inside the resulting architecture.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Hardware Implementation of Hybrid Classifier to Detect Cancer Cells 14

Hardware Implementation of Hybrid Classifier to Detect Cance...

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14th IEEE India Council international conference, INDICON 2017

作者： Gowda, M. Naresh Rasheed, Abdul Imran Department of Electronics and Communication Engineering M. S. Ramaiah University of Applied Sciences Bengaluru India

ISBN: (纸本)9781538643181

Convolutional Neural Network and Support Vector Machine are the common machine learning algorithms for classification. Both the classification techniques are fused to develop a hybrid classifier. The hardware implementation of hybrid classifier can improve the performance of the system and reduce the power consumption for real time applications. The main aim of this study is early detection of cancer cell using hybrid classifier implemented on a low cost handheld device. Leukemia and melanoma are the blood and skin cancer respectively. Both are dangerous form of cancers, many deaths have occurred due to leukemia and melanoma. In this paper, a hardware design is proposed to implement hybrid classifier on FPGA. The proposed system is implemented on Zync SoC FPGA platform and it gives the high performance, low power consumption and low hardware utilization. © 2017 IEEE.

关键词： field programmable gate arrays (FPGA)

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Blind Sparse Recovery From Superimposed Non-Linear Sensor Measurements 12

Blind Sparse Recovery From Superimposed Non-Linear Sensor Me...

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12th international conference on Sampling Theory and applications (SAMPTA)

作者： Genzel, Martin Jung, Peter Tech Univ Berlin Dept Math Berlin Germany Tech Univ Berlin Commun & Informat Theory Grp Berlin Germany

ISBN: (纸本)9781538615652

In this work, we study the problem of sparse recovery from superimposed, non-linearly distorted measurements. This challenge is particularly relevant to wireless sensor networks that consist of autonomous and spatially distributed sensor units. Here, each of the M wireless sensors acquires m individual measurements of an s-sparse source vector x(0) is an element of R-n. All devices transmit simultaneously to a central receiver, causing collisions. Since this process is imperfect, e.g., caused by low-quality sensors and the wireless channel, the receiver measures a superposition of corrupted signals. First, we will show that the source vector can be successfully recovered from m = O(s log(2n/s)) coherently communicated measurements via the vanilla Lasso. The more general situation of non-coherent communication can be approximated by a bilinear compressed sensing problem. Even in the non-linear setting, it will turn out that m = O(s . max{M, log(2n/s)}) measurements are already sufficient for reconstruction using the (group) l(1,2)-Lasso. In particular, as long as M = O(log(2n/s)) sensors are used, there is no substantial increase in performance when building a coherently communicating network. Finally, we shall discuss several practical implications and extensions of our approach.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Profiling BCI users based on contralateral activity to improve kinesthetic motor imagery detection 8

Profiling BCI users based on contralateral activity to impro...

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8th international IEEE/EMBS conference on Neural Engineering (NER)

作者： Rimbert, Sebastien Lindig-Leon, Cecilia Bougrain, Laurent INRIA Neurosys Team F-54600 Villers Les Nancy France Univ Lorraine Artificial Intelligence & Complex Syst LORIA UMR 7503 F-54506 Vandoeuvre Les Nancy France LORIA CNRS UMR 7503 Neurosys Team F-54506 Vandoeuvre Les Nancy France

ISBN: (纸本)9781509046034

Kinesthetic motor imagery (KMI) tasks induce brain oscillations over specific regions of the primary motor cortex within the contralateral hemisphere of the body part involved in the process. This activity can be measured through the analysis of electroencephalographic (EEG) recordings and is particularly interesting for Brain-Computer Interface (BCI) applications. The most common approach for classification consists of analyzing the signal during the course of the motor task within a frequency range including the alpha band, which attempts to detect the Event-Related Desynchronization (ERD) characteristics of the physiological phenomenon. However, to discriminate right-hand KMI and left-hand KMI, this scheme can lead to poor results on subjects for which the lateralization is not significant enough. To solve this problem, we propose that the signal be analyzed at the end of the motor imagery within a higher frequency range, which contains the EventRelated Synchronization (ERS). This study found that 6 out of 15 subjects have a higher classification rate after the KMI than during the KMI, due to a higher lateralization during this period. Thus, for this population we can obtain a significant improvement of 13% in classification taking into account the users lateralization profile.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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System on Chip Generation for Multi-Sensor and Sensor Fusion applications 17

System on Chip Generation for Multi-Sensor and Sensor Fusion...

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17th Annual international conference on Embedded Computer Systems - Architectures, Modeling, and Simulation (SAMOS)

作者： Lieske, Tobias Pfundt, Benjamin Vaas, Steffen Reichenbach, Marc Fey, Dietmar Friedrich Alexander Univ Erlangen Nurnberg FAU Chair Comp Architecture Dept Comp Sci Erlangen Germany

ISBN: (纸本)9781538634370

The amount of smart devices in our daily lives has dramatically increased. Many of these devices include sensors to capture their environment and communicate with other devices, forming the internet of things (IoT). A similar process of increasing intercommunication and digitization can be seen in industry where this development is called Industry 4.0. In this new era there is a strong demand for new computing architectures that fulfill the tight energy constraints as well as deliver enough on-chip processing performance. Off-the-shelf microcontrollers do not suffice both requirements as the power to performance ratio is too high. One solution are system on chip (SoC) architectures with domain specific application specific processors (ASIP). However, this new and competitive market requires a strongly reduced time to market. Thus, it is necessary to speed up the design process and deliver enough flexibility to adapt to new applications. Therefore, we propose a new SoC generation framework, which is based on an ASIP architecture. Architectural templates can be combined with existing intellectual property (IP) components, high-level synthesis (HLS) or hardware description language (HDL) code to speed up the design process. Both field programmable gate array (FPGA) and application specific integrated circuit (ASIC) back ends are supported. The architecture targets primarily multi-sensor and sensor fusion applications. A customizable MIPS processor with an adaptable compiler toolchain ensures interoperability in standard networks. The capabilities of our SoC architecture is demonstrated on two real world problems, including a performance demanding power quality monitoring application and a low-power swimming exercise tracking applications. Results show that the application constraints can be easily fulfilled while increasing speed and flexibility in the design process.

关键词： IoT SoC generation MIPS power quality monitoring biosignal processing

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