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检索条件"任意字段=International Conference on Field Programmable Logic and Applications"

共 16770 条记录，以下是4791-4800 订阅

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Energy Efficient Protocol to Supervise Overground Pipelines using WSN

Energy Efficient Protocol to Supervise Overground Pipelines ...

引用

IEEE international conference on Recent Trends in Electronics, Information & Communication Technology

作者： Neetu Verma Neha Pandey Prince Rajpoot Information Technology REC Ambedkar Nagar Akbarpur India

ISBN: (数字)9781538624401

ISBN: (纸本)9781538624418

Wireless Sensor Network (WSN) is a prominent field which is actively researched by many researchers. WSN is a network which contains the huge number of tiny wireless sensor nodes having ability of communication, signal processing, sensing the information from its domain and one of the important, transmitting the information to the sink node after performing some mathematical computations. It is widely used in different applications as directory control, ecology, military, health issues and miscellaneous parts of pipelines. Each node of the network has the different amount of energy and nodes lose their energy in receiving and transmitting information. Due to usability in remote areas, the energy of these sensor nodes can not be recharged again. So it is important to find out the way of saving energy of nodes in transmitting the sensed information. In pipelines, a WSN with non-rechargable sensor nodes is needed that is having the property of sensing and routing the information to sink. So that every abnormal activity can be reported to the sink. Since, it is a remote area so the data communication should be in efficient manner to increase the lifetime of WSN. In this paper, we consider an overground gas pipeline that is monitored underground, on the pipeline and around the pipeline. For this, we have designed an architecture of WSN to collect information about any abnormal activity using an energy efficient approach.

关键词： Pipelines Wireless sensor networks logic gates Data models Computer architecture Data communication Energy consumption

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Relational Query Processing on OpenCL-based FPGAs 26

Relational Query Processing on OpenCL-based FPGAs

引用

26th international conference on field-programmable logic and applications (FPL)

作者： Wang, Zeke Paul, Johns Ntu, Hui Yan Cheah He, Bingsheng Zhang, Wei Nanyang Technol Univ Singapore Singapore NUS Singapore Singapore HKUST Hong Kong Hong Kong Peoples R China

ISBN: (纸本)9782839918442

The release of OpenCL support for FPGAs represents a significant improvement in extending database applications to the reconfigurable domain. Taking advantage of the programmability offered by the OpenCL HLS tool, an OpenCL database can be easily ported and re-designed for FPGAs. A single SQL query in these database systems usually consists of multiple operators, and each one of these operators in turn consists of multiple OpenCL kernels. Due to the specific properties of FPGAs, each OpenCL kernel can have different FPGA-specific optimization combinations, in terms of CU (compute unit) and SIMD (kernel vectorization), which are critical to the overall performance of query processing. Due to the resource limitation of an FPGA image, our query plan also considers the possibility of using multiple FPGA images. In this paper, we propose an FPGA-specific cost model to determine the optimal query plan in less than one minute. In particular, the FPGA synthesis time is significantly reduced by avoiding the need to evaluate all the feasible query plans on real FPGAs. Our cost model has two components: unit cost and optimal query plan generation. The first component generates multiple (unit cost, resource utilization) pairs for each kernel. The second component employs a dynamic programming approach to generate the optimal query plan which considers the possibility of using multiple FPGA images. The experiments show that 1) our cost model can accurately predict the performance of each feasible query plan for the input query, and can guide the optimal query plan generation, 2) our optimized query plan achieves a performance speedup 1.5x-4x over the state-of-the-art query processing on OpenCL-based FPGAs.

关键词： field programmable gate arrays (FPGA)

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Organization of Data Exchange through the Modbus Network between the SIMATIC S7 PLC and field Devices

Organization of Data Exchange through the Modbus Network bet...

引用

international conference on Industrial Engineering, applications and Manufacturing (ICIEAM)

作者： Khuzyatov, Sh. Sh. Valiev, R. A. Kazan Fed Univ Naberezhnye Chelny Inst Kazan Russia

ISBN: (纸本)9781509056484

The method is suggested to establish master-slave communication between the Siemens PLC and field devices based on the Modbus protocol for process control systems. The data exchange between the PLC and current node in the network is organized by using the session data blocks. Creating the request package and unpacking the response from the slave device are carried out by the two respective functions made with the SCL language help in the Step 7 system. At the implementation of this method, the storing of the network and nodes characteristics as well as the data obtained from the network are implemented in additional data blocks of the network level which are the shared memory for the entire control system. This ensures their availability for both the PLC software and the visualization software. The using of the shared memory provides an ability to design a PLC program for data exchange through a network and for process control carried independently of each other which considerably simplifies the development of the process control system software.

关键词： automated control system programmable logic controller field device Modbus protocol network communication

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Design of a Compact and Reconfigurable Onboard Data Handling System

Design of a Compact and Reconfigurable Onboard Data Handling...

引用

IEEE international conference on Big Data and Cloud Computing (BdCloud)

作者： Qing Zhou Qingjie Zhao Li Zhou Junshe An Changbin Xue Yuyin Tan Jianing Rao National Space Science Center Chinese Academy of Sciences Beijing China Beijing Institute of Technology Beijing China

ISBN: (纸本)9781728111421;9781728111414

Onboard data handling (OBDH) system is the key to spacecraft avionics. To adapt to the harsh external space environment, traditional onboard data handling system is usually highly expensive, complex and arduous by using high quality components. Design of a compact and reconfigurable onboard data handling system based is proposed in this paper. A NOR Flash with mass storage is designed as the program memory for CPU and SRAM FPGAs. The programs of the CPU and SRAM FPGAs in this system can still be reconfigurable for the launched satellites. Rad-hard designs from the Software and hardware are adopted in the onboard data handling system to realize the performances of high reliability, anti-SEU(single event upset) effect, software reconfiguration with less mass, volume and cost. Some experimental results are shown at last in the system verification.

关键词： field programmable gate arrays Random access memory Software Data handling Aerospace electronics Software reliability

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On the Information Selection for Optimal Data Association 20

On the Information Selection for Optimal Data Association

引用

20th international conference on Information Fusion (Fusion)

作者： Laghmara, Hind Cudel, Christophe Lauffenburger, Jean-Philippe Boumediene, Mohammed Univ Haute Alsace Lab MIPS EA2332 Mulhouse France Inst Natl Telecommun & Technol Informat & Commun Oran Algeria

ISBN: (纸本)9780996452700

Multiple Object Association (MOA) is an essential process in making vehicles smarter. It consists in associating newly detected objects to previously known ones at each instant in a scene. To treat such matter, the paper proceeds by the use of the Belief Theory introduced by Dempster-Shafer. A crucial concern in this application is the data association complexity and its relative computation time which must be distinguishably minimized. For that, this paper proposes a new approach in order to fit to real-time Intelligent Transportation Systems (ITS) applications. The solution consists in a first step on selecting the sources which deliver the most pertinent information and in the second step to combine the reduced data set. The effectiveness in the association quality as well as in the complexity reduction is shown with a pedestrian tracking example from the KITTI vision benchmark.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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FPGA based Implementation of Brushless DC Motor Drive using Single Current Sensor and Comparison with Conventional Method

FPGA based Implementation of Brushless DC Motor Drive using ...

引用

IEEE international conference on Power, Control, Signals and Instrumentation Engineering (IEEE ICPCSI)

作者： Babu, Jithin Radhika, R. Govt RIT Kottayam Dept Elect & Elect Kottayam Kerala India

ISBN: (纸本)9781538608142

The brushless DC (BLDC) motors being the most common choice in electrical drives, has increasing popularity due to its higher efficiency, greater reliability, good dynamic response, low power, high speed and very low maintenance. For closed-loop current control of BLDC motors, phase currents are measured with appropriate current sensors. Such current sensors are bulky, heavy and expensive for the drive applications which limits its wide usage. More over the use of more than two current sensors can cause unwanted disturbances in phase currents and torque pulsation due to mismatches in the phase current sensor sensitivity which may cause the poor performance and reliability of the system. This paper focus to overcome these problems by a new single current sensor strategy for phase current control of BLDC motor drives. The controller is modelled and the concept is proven using MATLAB/ XILINX simulator. The effectiveness of the new proposed control strategy has been validated by comparative studies of simulation results of conventional and proposed methods. The performance analysis and the validation of the hardware setup is done using field-programmable gate array (FPGA) prototyping.

关键词： Brushless DC (BLDC) motor single current control EMF(Electro Motive Force) PI(Propotional-Integral) Controller

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Design of optimized FIR filter using Radix-2~r

Design of optimized FIR filter using Radix-2~r

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IEEE international conference on Recent Trends in Electronics, Information & Communication Technology

作者： D Saketh Vishnu P Nikhila Reddy D V Sowjanya Swaminadhan Rajula Electronics & Communication Engineering Amrita School of Engineering Amrita Vishwa Vidyapeetham

ISBN: (数字)9781538624401

ISBN: (纸本)9781538624418

Finite Impulse Response (FIR) filters are mainly used in the Digital Signal Processing (DSP) applications. The main reason behind implementing FIR filters is because of its high speed and low power requirements. The main complexity of designing FIR filter lies in the multiplier block. There are many techniques by using add and shift operations exclusively through which we can actually design the multiplier block thus reducing the complex structure of multiplier and these type of designs are called multiplier-less. A New Multiple Constant Multiplication algorithm (MCM) called Radix-2~r has merit over existing algorithms for being fully predictable, sub linear, high speed and low power solutions. This paper presents the designing of an FIR filter using radix-2~r recoding technique with 'r=5' and a unique Lookup Table for it and also being implemented further. The proposed design gives the better results compared to normal design in terms of adder-cost, adder depth & resource utilization and corresponding trade-off occurs between delay & resource utilization.

关键词： FIR filter Add and shift operations Multiplier-less MCM Radix-2~r Look-up table FPGA FIR filters Multichip modules Multicarrier modulation field programmable gate arrays Multiplying circuits PUF60 gene FARP2 gene color lookup table Filters Table lookup High speed Resource utilization Digital signal processing power requirement

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Soft Computing applications: Proceedings of the 7th international Workshop Soft Computing applications (SOFA 2016), Volume 2

引用

2017年

作者： Valentina Emilia Balas Lakhmi C Jain Marius Mircea Balas

ISBN: (纸本)9783319625232

These two volumes constitute the Proceedings of the 7th international Workshop on Soft Computing applications (SOFA 2016), held on 2426 August 2016 in Arad, Romania. This edition was organized by Aurel Vlaicu University of Arad, Romania, University of Belgrade, Serbia, in conjunction with the Institute of Computer Science, Iasi Branch of the Romanian Academy, IEEE Romanian Section, Romanian Society of Control Engineering and Technical Informatics (SRAIT) - Arad Section, General Association of Engineers in Romania - Arad Section, and BTM Resources Arad. The soft computing concept was introduced by Lotfi Zadeh in 1991 and serves to highlight the emergence of computing methodologies in which the accent is on exploiting the tolerance for imprecision and uncertainty to achieve tractability, robustness and lower costs. Soft computing facilitates the combined use of fuzzy logic, neurocomputing, evolutionary computing and probabilistic computing, leading to the concept of hybrid intelligent systems. The rapid emergence of new tools and applications calls for a synergy of scientific and technological disciplines in order to reveal the great potential of soft computing in all domains. The conference papers included in these proceedings, published post-conference, were grouped into the following areas of research: Methods and applications in Electrical Engineering Knowledge-Based Technologies for Web applications, Cloud Computing, Security Algorithms and Computer Networks Biomedical applications Image, Text and Signal Processing Machine Learning and applications Business Process Management Fuzzy applications, Theory and Fuzzy Control Computational Intelligence in Education Soft Computing & Fuzzy logic in Biometrics (SCFLB) Soft Computing Algorithms Applied in Economy, Industry and Communication Technology Modelling and applications in Textiles The book helps to disseminate advances in selected active research directions in the field of soft computing, along with current issues

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Fair Decentralized Data-Rate Congestion Control for V2V Communications 24

Fair Decentralized Data-Rate Congestion Control for V2V Comm...

引用

24th international conference on Telecommunications (ICT)

作者： Math, Chetan Belagal Li, Hong de Groot, Sonia Heemstra Niemegeers, Ignas Eindhoven Univ Technol Elect Engn Eindhoven Netherlands NXP Semicond Car Infotainment & Driving Assistance Eindhoven Netherlands

ISBN: (纸本)9781538606438

Channel congestion is one of the most critical issues in IEEE 802.11p-based vehicular ad hoc networks because congestion may lead to unreliability of applications. As a counter measure, the European Telecommunications Standard Institute (ETSI), proposes a mandatory Decentralized Congestion Control (DCC) framework to control the channel load. DCC algorithms are proposed to tune parameters such as message-rate, data-rate, etc. to avoid congestion. An important requirement for DCC algorithms is fairness, which ensures that vehicles experiencing similar channel loads are entitled to similar transmission parameters, in particular, message-rate and data-rate. Message-rate DCC (LIMERIC) ensures a fair message-rate selection, while data-rate DCC (DR-DCC) might end up with different data-rates, creating unfairness among the vehicles: vehicles with lower data-rate have a larger communication range than those using higher data-rates. Therefore some vehicles are less visible than others, which is detrimental to the reliability of the safety applications. To avoid this, the paper defines a novel packet-count based decentralized data-rate congestion control algorithm (PDR-DCC), which enforces fairness and hence improves the application-reliability. Simulation studies are performed to demonstrate that PDR-DCC avoids congestion in a fair manner. We also show the effect of fairness on the application-reliability by comparing the performance of PDR-DCC with message-rate (LIMERIC) and data-rate (DR-DCC) congestion control algorithms for a stationary vehicle warning application in a synthetic highway scenario and for various vehicular densities. We conclude that PDR-DCC outperforms LIMERIC, and DR-DCC in terms of application-reliability.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Heterogeneous computing system platform for high-performance pattern recognition applications 6

Heterogeneous computing system platform for high-performance...

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6th international conference on Modern Circuits and Systems Technologies (MOCAST)

作者： Mirzaei, M. Ali Voisin, Vincent Annovi, Alberto Baulieu, Guillaume Beretta, Matteo Calderini, Giovanni Citraro, Saverio Crescioli, Francesco Galbit, Geoffrey Liberali, Valentino Shojaii, Seyed Ruhollah Stabile, Alberto Tromeur, William Viret, Sebastien CNRS UPMC IN2P3 LPNHE 4 Pl Jussieu F-75005 Paris France CNRS IN2P3 IPNL UCBL 4 Rue Enrico Fermi F-69622 Villeurbanne France Univ Pisa INFN Pisa Largo B Pontecorvo 3 I-56127 Pisa Italy Univ Milan INFN Milano Via Celoria 16 I-20133 Milan Italy Ist Nazl Fis Nucl Lab Nazl Frascati Via Enrico Fermi 40 I-00044 Frascati Italy

ISBN: (纸本)9781509043866

we present a system architecture made of a motherboard with a Xilinx Zynq System on Chip (SoC) and a mezzanine board equipped with an Associative Memory chip (AM). The proposed architecture is designed to serve as an accelerator of general purpose algorithms based on pipeline processing and pattern recognition. We present the open source software and firmware developed to fully exploit the available communication channels between the ARM CPU and the FPGA using Direct Memory Access (DMA) technique and the AM using Multi-Gigabit Transceivers (MGT). We report the measured performances and discuss potential applications and future developments. The proposed architecture is compact, portable and provide a large communication bandwidth between components.

关键词： field programmable gate arrays Program processors Linux Computer architecture Communication channels Central Processing Unit Standards

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