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检索条件"任意字段=International Conference on Field Programmable Logic and Applications"

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Adaptive Control Technique for Generator Side Power System Voltage Stability at Wind Power Station 2nd

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2nd international conference on Intelligent Computing and applications (ICICA)

作者： Nave, M. Presh Priyatharshini, K. Nijandhan, N. Pradeep, S. KCG Coll Technol Dept EEE Madras Tamil Nadu India PA Coll Engn Dept ECE Pollachi India

ISBN: (纸本)9789811016455;9789811016448

Voltage instability and over voltage are one of the main problems in today wind industry. In wind power production system the output is depends upon the nature of source called wind. But that source is not constant one. It may be varying depending upon the climate. Due to that oscillation the output voltage from the generator side is instability. These problems are becoming a more serious concern with the ever-increasing utilization and higher loading of existing transmission systems, particularly with increasing energy wastage, energy demands, and competitive generation and supply requirements. Our aim is to improve power system voltage stability by enhancing generator reactive, active power control and voltage control. Adaptive feedback system along with the HSVC ways to improve power system voltage stability by enhancing generator controls in the wind power station. To solve this problem adaptive exciter system are used which will adjust the load voltage and the system voltage with that of the reference voltage. The generator output voltage is applied to the adaptive exciter controller (AEC) which updates its stability weight value on demand. The design of modules can be done in Xilinx system generator (XSG). The modules that are designed in system generator can be implemented in FPGA.

关键词： Advanced over-excitation limiters High side voltage control Adjustable speed machines Adaptive linear network Adaptive exciter controller Xilinx system generator field programmable gate array

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An area efficient high speed optimized FFT algorithm 4

An area efficient high speed optimized FFT algorithm

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4th international conference on Signal Processing, Communication and Networking (ICSCN)

作者： Manuel, Betsy Rose Konguvel, E. Kannan, M. Anna Univ Dept Elect Engn Madras Inst Technol Madras 600044 Tamil Nadu India

ISBN: (纸本)9781509047406

In recent years the Fast Fourier Transform is widely used in a number of applications as it is considered to be an efficient algorithm to compute the Discrete Fourier Transform. The process of computing the FFT for large sequence real time data becomes complex and tedious. Hence it is necessary to design a system that can perform the FFT computation of large sequence data with reduced power consumption. This paper presents the design of low power Radix-8 DIT FFT. The proposed design aims at reducing the number of multipliers that are used to compute the FFT. This is achieved by swapping the input terms and reordering them. This leads to a reduction in the number of multipliers used to perform the computation and thereby causing a reduction in the power consumption. This method is highly advantageous when the input signals are lengthy since the number of multipliers used is large in number consuming very high power. In order to optimize the FFT architecture the number of multipliers is reduced thereby causing a significant reduction in power. The prototype for Radix-2 (8 point) and Radix-4 (16 point) optimized FFT is designed, implemented and simulated using Altera ModelSim DE2 EP2C35F672C6 FPGA device. The proposed Radix-2 (8 point) and Radix-4 (16 point) optimized FFT operates at a speed of 10.41 Gbps and 21.23 Gbps respectively.

关键词： Split Radix Fourier Transform (SRFT) field programmable Gate Array (FPGA) Multiple Input Multiple Output (MIMO) Orthogonal Frequency Division Multiplexing (OFDM) Floating Point (FP) Fast Fourier Transform (FFT) Decimation in time (DIT)

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Area Efficient Dataflow Hardware Design of SAO Filter for HEVC 3

Area Efficient Dataflow Hardware Design of SAO Filter for HE...

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international conference on Innovations in Electronics, Signal Processing and Communication (IESC)

作者： Shukla, Kaustubh Swamy, Baldev Rangababu, P. Maharaja Surajmal Inst Technol Elect & Commun Engn Delhi India Natl Inst Technol Meghalaya Elect & Commun Engn Shillong Meghalaya India

ISBN: (纸本)9781509056200

This paper presents the Area Efficient Dataflow Hardware Design of Sample Adaptive Offset filter (SAO) for High Efficiency Video Coding (HEVC). The proposed SAO filter architecture is designed to utilize least amount of resources which minimizes chip area and yields high synthesis frequency as is required for 4kx2k decoding/encoding based applications. The proposed filter is designed to work with a 64x64 de-blocked Coding Tree Unit (CTU) block which is enhanced to 66x66 to include the boundary pixels. The proposed SAO filter is based on the sequential access of pixels obtained from DBF using a control path. These values are filtered and mapped to 64x64 CTU and finally written in memory. The proposed SAO filter design is implemented on FPGA platform (Virtex-6-lx240T). The synthesized frequency is obtained as 100MHz in ASIC platform. The chip layout area is 15585.328 mu m(2) and gate count is 5k. The resource consumption is less as compared to literature works.

关键词： Edge Offset (EO) Band Offset (BO) Coding Tree Unit (CTU) Sample Adaptive Offset (SAO) Deblocking Filter (DBF) ROM (Read Only Memory) ASIC (Application Specific Integrated Circuit) FPGA (field programmable Gate Array)

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Area efficient lagrange image up scaling architecture for multimedia applications

Area efficient lagrange image up scaling architecture for mu...

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2017 IEEE international conference on Signal Processing and Communication, ICSPC 2017

作者： Moses, C John Selvathi, D. Queen, G Sahaya Edal Dept. of ECE St. Xavier's Catholic College of Engineering Nagercoil India Dept. of ECE Mepco Schlenk Engineering College Sivakasi India

ISBN: (纸本)9781509067305

Interpolation is the process of constructing new pixels from the known pixels in an image. This work presents an area efficient up-scaling architecture of Lagrange interpolation for digital image. Lagrange interpolation is widely used to get high visual quality. It is a technique to estimate the unknown pixel values from the given pixels. It provides high estimation accuracy and fewer additions and shift operations are needed to calculate the weighting coefficients. To enhance the visual quality, clamp filter is implemented with the interpolation technique. It is used to preserve the edge information. The Hardware architecture of Bi-cubic, Lagrange interpolation algorithm and clamp filter based bi-cubic, Lagrange interpolation algorithm for various kernels such as 3×3 kernel, cross model, 2×3 model and T-model was simulated in MATLAB Simulink and Xilinx ISE generator. Among this various kernels of clamp filter, T model clamp filter with Lagrange interpolation achieved 10.52% reduction in LUTs compared to Bi-cubic interpolation algorithm. © 2017 IEEE.

关键词： field programmable gate arrays (FPGA)

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Hardware accelerators for Recurrent Neural Networks on FPGA 50

Hardware accelerators for Recurrent Neural Networks on FPGA

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IEEE international Symposium on Circuits and Systems (ISCAS)

作者： Chang, Andre Xian Ming Culurciello, Eugenio Purdue Univ Dept Elect & Comp Engn W Lafayette IN 47907 USA

ISBN: (纸本)9781467368537

Recurrent Neural Networks (RNNs) have the ability to retain memory and learn from data sequences, which are fundamental for real-time applications. RNN computations offer limited data reuse, which leads to high data traffic. This translates into high off-chip memory bandwidth or large internal storage requirement to achieve high performance. Exploiting parallelism in RNN computations are bounded by this two limiting factors, among other constraints present in embedded systems. Therefore, balance between internally stored data and off-chip memory data transfer is necessary to overlap computation time with data transfer latency. In this paper, we present three hardware accelerators for RNN on Xilinx's Zynq SoC FPGA to present how to overcome challenges involved in developing RNN accelerators. Each design uses different strategies to achieve high performance and scalability. Each co-processor was tested with a character level language model. The latest design called DeepRnn, achieves up to 23x better performance per power than Tegra X1 development board for this application.

关键词： logic gates Bandwidth Hardware field programmable gate arrays Computer architecture Data transfer System-on-chip

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CP-TPS: A real-time transaction processing strategy supporting compensatory task 20

CP-TPS: A real-time transaction processing strategy supporti...

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20th IEEE international conference on Computational Science and Engineering (CSE) / 15th IEEE/IFIP international conference on Embedded and Ubiquitous Computing (EUC)

作者： Wang, Wenle Cao, Yuanlong Gong, Jun Li, Zhifen Jiangxi Normal Univ Sch Software Nanchang 330022 Jiangxi Peoples R China

ISBN: (纸本)9781538632215

In embedded applications, some real-time transactions may trigger external device. If these transactions fail, the influence caused by the triggered external device should be removed. The real-time database can't eliminate the influence, then we exploit compensatory task to compensate for the external influences. In this paper, the real-time transaction is divided into two parts: main task and compensatory task. According to the degree of external influence, it was classified as three types: criticalimportant and non-influence. Accordingly, the compensatory task's degree mainly include three levels: level CI, level CII and level CIII. The compensatory processing-transaction processing strategy (CP-TPS) is proposed to schedule tasks. For the tasks at different levels, they are compensated at different times by CP-TPS as follows: 1) For CI level task, once the abort probability of it reach the threshold, the compensatory task starts to compensate immediately;2) For CII level task, the compensatory task starts after the main task aborted;3) For the task at level CII, the compensatory task starts when the system is idle. Experiments indicate that the system using CP-TPS strategy can reduce the Miss Deadline Rtio (MDR), also it can increase the Effective Utilization Ratio (EUR) and the Total Value (TV).

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Fabrication of Low-OH GeS₂ Glasses and Multimode Fibres for Mid-IR applications 19

Fabrication of Low-OH GeS<sub>2</sub> Glasses and Multimode ...

引用

19th international conference on Transparent Optical Networks (ICTON)

作者： Hill, Clare J. Jha, Animesh Univ Leeds Ctr Funct Mat Sch Chem & Proc Engn Leeds LS2 9JT W Yorkshire England Pilkington Technol Ctr NSG Grp Hall Lane Lathom L40 5UF Ormskirk England

ISBN: (纸本)9781538608593

The fabrication properties of ternary and quaternary GeS2-based chalcogenide glasses are discussed in view of the removal impurities and control of crystallization by controlling the starting composition, raw materials purification and fabrication steps. The two specific compositions discussed for glass and fibre fabrication are: GeS2-Ga2S3-CsI and GeS2-Ga2S3-CsI-SnS which were optimised for multimode fibre fabrication by investigating the thermal and viscosity properties. For chemical process control in food, pharmaceutical and petrochemical industry, optical fibre sensors operating above 200 degrees C in chemical process environment are required. For food and pharmaceutical it is also safer to use materials which are non-toxic. With these aims in mind we focussed on designing the glass structure by raising the T-g from 350 degrees C in ternary glass composition to 450 degrees C. By modifying the glass structure with the addition of SnS, the probability of near-T-g and sub-T-g structural relaxation in optical fibres, derived from quaternary compositions. For the analysis of structural modification in glass, we have systematically carried out Raman spectroscopy using 514 and 633 nm sources. We report changes in the structure as a function of composition. The Raman spectroscopic analysis is also complemented by the IR reflection and transmission spectroscopy for a more comprehensive characterisation the vibrational structures. The glass compositions were also analysed for their devitrification and near T-g relaxation behaviour. On the basis of the devitrification characteristics we have also characterised the thermal stabilities of various compositions under thermal cyclic loading in the transformation region. The structural relaxation behaviour above T-g was also characterised by using a differential mechanical analyser by measuring the viscosity.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Patterns System for the Design of Partial Reconfigurable applications on FPGA 12

Patterns System for the Design of Partial Reconfigurable App...

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12th international conference on Evaluation of Novel Approaches to Software Engineering (ENASE)

作者： Fredj, Nissaf Saidane, Mhamed Kacem, Yessine Hadj Abid, Mohamed ENIS ISITCOM CES Lab Sfax Tunisia ENIS CES Lab Sfax Tunisia TIM Lab Monastir Tunisia King Khalid Univ Coll Comp Sci Abha Saudi Arabia

ISBN: (纸本)9789897582509

During the last few years, the Dynamic Partial Reconfiguration (DPR) has been introduced to the embedded systems as a key technique that aims at improving the flexibility of field-programmable Gate Array (FPGA)-based system reconfiguration. However, the design of these systems is a hard task using low-level functions where the design of the hardware side precedes that of the software. Recently, Model-Driven Engineering (MDE) based approaches have emerged. They aim at simplifying the modeling of the dynamically set systems and keep a design flow where DPR application and architecture are designed in parallel. In fact, there is a lack of reusable and generic models that allow the improvement of the designers' task and the decrease of the development costs. In order to overcome these issues we propose in this paper an additional featuring or abstraction level in the DPR design flow introduced by these approaches. Our aim is to suggest for designers a method (process and models) which allows reusing recurrent application models and sharing experience-owned knowledge. The proposed method is a patterns system which is a combination of architectural and behavioral patterns dedicated to the Dynamic Partial reconfigurable Real-Time Embedded (DP-RTE) systems.

关键词： DPR Patterns System Behavioral Pattern Architectural Pattern DP-RTE Systems

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A Rapid Data Communication Exploration Tool for Hybrid CPU-FPGA Architectures 25

A Rapid Data Communication Exploration Tool for Hybrid CPU-F...

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25th Euromicro international conference on Parallel, Distributed and Network-Based Processing (PDP)

作者： Makni, Mariem Niar, Smail Baklouti, Mouna Zhong, Guanwen Mitra, Tulika Abid, Mohamed Univ Valenciennes LAMIH Valenciennes France Natl Engn Sch Sfax Sfax Tunisia Natl Univ Singapore Singapore Singapore

ISBN: (纸本)9781509060580

Modern System-on-Chip (SoC) designs face many challenges. Choosing the best communication protocol among the different processing nodes is one of the most important design decisions. On-chip communication architectures can have a significant impact on the performance of SoC designs. However, in most of the existing design tools, only the computation cost is accurately estimated. To address this challenge, we present a high-level analytical tool to estimate the data communication cost for hybrid CPU-FPGA architectures. The proposed model allows to estimate, rapidly and accurately, both computation and communication cost of applications containing multiple nested loops. This paper also explores the benefits of applying various optimization pragmas including dataflow and loop pipelining, at the compilation phase. Experimental results show that the proposed model provides accurate data communication estimation for hybrid CPUFPGA architectures.

关键词： Kernel Data communication Estimation Computational modeling Pipeline processing Analytical models field programmable gate arrays

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2017 3rd international conference on Event-Based Control, Communication and Signal Processing, EBCCSP 2017 - Proceedings

2017 3rd International Conference on Event-Based Control, Co...

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3rd international conference on Event-Based Control, Communication and Signal Processing, EBCCSP 2017

ISBN: (纸本)9781538609156

The proceedings contain 30 papers. The topics discussed include: four-channel, precise, time-event recorder in programmable device;dynamic equalization of logic delays in feedback-based successive approximation TDCs;frequency-domain adaptive-resolution level-crossing-sampling ADC;oscillator-based ADCs: an exploration of time-mode analog-to-digital conversion;unified enhanced time petri net models for development of the reactive applications;estimating the signal reconstruction error from threshold-based sampling without knowing the original signal;amplitude adaptive ASDM circuit;recoverability of band-passed signals from non-zero threshold crossings;implementing state machines in distributed event-based systems;model-based source coding of dynamical cyber-physical systems;secured event-based smart meter;efficient protocol design and scheduling in networked control systems based on compressed sensing;preliminary research on predictive sparse reporting in low-voltage network PLC-based metering;global sensitivity criteria and Haar wavelet in smart grid modelling;Industry 4.0: application scenarios and the impact of control and automation;a panoramic overview of event based control: a retrospective look from the seventies;and suboptimal event-triggered control over unreliable communication links with experimental validation.

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