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检索条件"任意字段=International Conference on Field Programmable Logic and Applications"

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Implementation of a scalable real time canny edge detector on programmable SOC

Implementation of a scalable real time canny edge detector o...

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international conference on Electrical and Computing Technologies and applications (ICECTA)

作者： Bhagesh C. Maheshwari John Burns Michaela Blott Giulio Gambardella Department of Computing Institute of Technology Tallaght Dublin Ireland Research Labs Ireland Xilinx Inc Dublin Ireland

ISBN: (纸本)9781538608739

In today's world, we are surrounded by variety of computer vision applications e.g. medical imaging, bio-metrics, security, surveillance and robotics. Most of these applications require real time processing of a single image or sequence of images. This real time image/video processing requires high computational power and specialized hardware architecture and can't be achieved using general purpose CPUs. In this paper, a FPGA based generic canny edge detector is introduced. Edge detection is one of the basic steps in image processing, image analysis, image pattern recognition, and computer vision. We have implemented a re-sizable canny edge detector IP on programmable logic (PL) of PYNQ-Platform. The IP is integrated with HDMI input/output blocks and can process 1080p input video stream at 60 frames per second. As mentioned the canny edge detection IP is scalable with respect to frame size i.e. depending on the input frame size, the hardware architecture can be scaled up or down by changing the template parameters. The offloading of canny edge detection from PS to PL causes the CPU usage to drop from about 100% to 0%. Moreover, hardware based edge detector runs about 14 times faster than the software based edge detector running on Cortex-A9 ARM processor.

关键词： Image edge detection Detectors Hardware Streaming media field programmable gate arrays Real-time systems Algorithm design and analysis

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Exploring Optimized Accelerator Design for Binarized Convolutional Neural Networks

Exploring Optimized Accelerator Design for Binarized Convolu...

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international Joint conference on Neural Networks

作者： Kodai Ueyoshi Kota Ando Kentaro Orimo Masayuki Ikebe Tetsuya Asai Masato Motomura Hokkaido University Graduate School of Information Science and Technology Sapporo Hokkaido 060-0814 Japan

ISBN: (纸本)9781509061839

The convolutional neural network (CNN) is a state-of-the-art model that can achieve significantly high accuracy in many machine-learning tasks. Recently, for further developing the practical applications of CNNs, efficient hardware platforms for accelerating CNN have been throughly studied. A binarized neural network has been reported to minimize the multipliers, which consume a large amount of resources, with a minimal decrease in accuracy. In this study, we analyzed the optimal performance of CNN implemented on an field programmable gate array (FPGA) considering its logic resources and a memory bandwidth, using multiple types of parallelisms such as kernels, pixels, and channels both in conventional and binarized CNNs. As a result, it became clear that all the parallelisms are required for the binarized neural network to obtain the best performance of 8.38 TOPS.

关键词： Parallel processing Bandwidth Kernel Digital signal processing Biological neural networks field programmable gate arrays

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Adaptable VLIW processor: The reconfigurable technology approach 10

Adaptable VLIW processor: The reconfigurable technology appr...

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10th international conference on Advanced Technologies for Communications, ATC 2017

作者： Pham-Quoc, Cuong Kieu-Do-Nguyen, Binh Dinh-Duc, Anh-Vu Ho Chi Minh City University of Technology VNU-HCM Viet Nam Vietnam National University Ho Chi Minh City Viet Nam

ISBN: (纸本)9781538628966

Traditional processor design approaches using CISC and RISC philosophies suffer from low performance. One of alternative approaches to improve system performance is instruction level parallelism (ILP). Among the processor architectures supporting ILP, very long instruction word (VLIW) processors offer some advantages such as low power consumption and hardware complexity. In this paper, we introduce our adaptable VLIW processor that can adapt its functionality and organization at design time so that the processor configuration is optimized for a specific application. Based on the reconfigurable technology approach, we propose our design framework that allows users to configure the VLIW processor according to parallelism level of a particular application. The design framework also helps designers implement the processor on FPGA platforms without knowing HDLs. We conduct our experiments by synthesizing the proposed VLIW processor with four different FPGA families and by developing three applications using our proposed VLIW processor. The synthesis results show that our processor can work at up 174.89 MHz when implemented with the Xilinx Virtex 7 FPGA devices. The experimental results show that the proposed VLIW processor can achieve speed-ups by up to 22.6× when compared to the NIOS II RISC-like softcore processor at the same working frequency. © 2017 IEEE.

关键词： field programmable gate arrays (FPGA)

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Uncertainty-driven Ensemble Forecasting of QoS in Software Defined Networks

Uncertainty-driven Ensemble Forecasting of QoS in Software D...

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IEEE Symposium on Computers and Communications (ISCC)

作者： Kolomvatsos, Kostas Anagnostopoulos, Christos Marnerides, Angelos K. Ni, Qiang Hadjiefthymiades, Stathes Pezaros, Dimitrios P. Univ Thessaly Dept Comp Sci Lamia 35100 Greece Univ Glasgow Sch Comp Sci Glasgow G12 8QQ Lanark Scotland Univ Lancaster Sch Comp & Commun InfoLab21 Lancaster LA1 4WA England Univ Athens Dept Informat & Telecommun Athens 15784 Greece

ISBN: (纸本)9781538616291

Software Defined Networking (SDN) is the key technology for combining networking and Cloud solutions to provide novel applications. SDN offers a number of advantages as the existing resources can be virtualized and orchestrated to provide new services to the end users. Such a technology should be accompanied by powerful mechanisms that ensure the end-to-end quality of service at high levels, thus, enabling support for complex applications that satisfy end users needs. In this paper, we propose an intelligent mechanism that agglomerates the benefits of SDNs with real-time 'Big Data' forecasting analytics. The proposed mechanism, as part of the SDN controller, supports predictive intelligence by monitoring a set of network performance parameters, forecasting their future values, and deriving indications on potential service quality violations. By treating the performance measurements as time-series, our mechanism employs a novel ensemble forecasting methodology to estimate their future values. Such predictions are fed to a Type-2 Fuzzy logic system to deliver, in real-time, decisions related to service quality violations. Such decisions proactively assist the SDN controller for providing the best possible orchestration of the virtualized resources. We evaluate the proposed mechanism w.r.t. precision and recall metrics over synthetic data.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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A Novel Approach for Coverage Probing of Embedded Software in SoPC

A Novel Approach for Coverage Probing of Embedded Software i...

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international conference on Dependable Systems and Their applications (DSA)

作者： Lu Kong Bin Wang Shan Zhou YaWen Yang Technology and Engineering Center for Space Utilization Chinese Academy of Sciences Beijing P.R. China

A novel approach is present to obtain coverage data of both embedded software and field programmable Gate Array (FPGA) program running in the System-on-programmable-Chip (SoPC) system. This approach integrates technologies of program instrumentation and traditional digital simulation, and improves the verification process by hardware acceleration. In order to verify the efficiency of the proposed approach, we have implemented it to a SoPC system which is employed for aviation applications. Statement and branch coverage of both FPGA program as well as embedded software have been obtained simultaneously during the verification. According to the case study, the proposed approach for coverage probing has excellent performance in SoPC verification.

关键词： field programmable gate arrays Embedded software Hardware design languages Instruments Acceleration Computational modeling Testing

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A formal semantics of SQL queries, its validation, and applications 44th

A formal semantics of SQL queries, its validation, and appli...

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44th international conference on Very Large Data Bases, VLDB 2018

作者： Guagliardo, Paolo Libkin, Leonid School of Informatics University of Edinburgh United Kingdom

While formal semantics of theoretical languages underlying SQL have been provided in the past, they all made simplifying assumptions ranging from changes in the syntax to omitting bag semantics and nulls. This situation is reminiscent of what happens in the field of programming languages, where semantics of formal calculi underlying the main features of languages are abundant, but formal semantics of real languages that people use are few and far between. We consider the basic class of SQL queries - essentially SELECT-FROM-WHERE queries with subqueries, set/bag operations, and nulls - and define a formal semantics for it, without any departures from the real language. This fragment already requires decisions related to the data model and handling variable names that are normally disregarded by simplified semantics. To justify our choice of the semantics, we validate it experimentally on a large number of randomly generated queries and databases. We give two applications of the semantics. One is the first formal proof of the equivalence of basic SQL and relational algebra that extends to bag semantics and nulls. The other application looks at the three-valued logic employed by SQL, which is universally assumed to be necessary to handle nulls. We prove however that this is not so, as three-valued logic does not add expressive power: every SQL query in our fragment can be evaluated under the usual two-valued Boolean semantics of conditions. © 2018 VLDB.

关键词： Semantics

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Scaling Binarized neural networks on reconfigurable logic 17

Scaling Binarized neural networks on reconfigurable logic

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8th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 6th Workshop on Design Tools and Architectures For Multicore Embedded Computing Platforms, PARMA-DITAM 2017

作者： Fraser, Nicholas J. Umuroglu, Yaman Gambardella, Giulio Blott, Michaela Leong, Philip Jahre, Magnus Vissers, Kees Xilinx Research Labs United States Norwegian University of Science and Technology Norway University of Sydney Australia

ISBN: (纸本)9781450348775

Binarized neural networks (BNNs) are gaining interest in the deep learning community due to their significantly lower computational and memory cost. They are particularly well suited to reconfigurable logic devices, which contain an abundance of fine-grained compute resources and can result in smaller, lower power implementations, or conversely in higher classification rates. Towards this end, the Finn framework was recently proposed for building fast and flexible field programmable gate array (FPGA) accelerators for BNNs. Finn utilized a novel set of optimizations that enable efficient mapping of BNNs to hardware and implemented fully connected, non-padded convolutional and pooling layers, with per-layer compute resources being tailored to user-provided throughput requirements. However, FINN was not evaluated on larger topologies due to the size of the chosen FPGA, and exhibited decreased accuracy due to lack of padding. In this paper, we improve upon Finn to show how padding can be employed on BNNs while still maintaining a 1-bit datapath and high accuracy. Based on this technique, we demonstrate numerous experiments to illustrate flexibility and scalability of the approach. In particular, we show that a large BNN requiring 1.2 billion operations per frame running on an ADM-PCIE-8K5 platform can classify images at 12 kFPS with 671 μs latency while drawing less than 41 W board power and classifying CIFAR-10 images at 88.7% accuracy. Our implementation of this network achieves 14.8 trillion operations per second. We believe this is the fastest classification rate reported to date on this benchmark at this level of accuracy. © 2017 ACM.

关键词： logic devices

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Applying models of computation to OpenCL pipes for FPGA computing 2017

Applying models of computation to OpenCL pipes for FPGA comp...

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5th international Workshop on OpenCL, IWOCL 2017

作者： Kapre, Nachiket Patel, Hiren University of Waterloo WaterlooONN2L 3G1 Canada

ISBN: (纸本)9781450352147

OpenCL pipes offer a powerful construct for synthesizing multikernel FPGA applications with inter-kernel communication dependencies. The communication discipline between the FPGA kernels is restricted to producer-consumer style patterns supported with on-chip FPGA FIFOs. While this provides few restrictions on the usage, the OpenCL compiler is unable to provide guarantees on buffering capacity or schedulability of the connected kernels. Without these guarantees, an OpenCL developer may over-provision hardware resources or assume pessimistic timing during scheduling. We propose imposing a communication discipline inspired from models of computation (***) such as synchronous dataflow (SDF), and bulk synchronous (BSP). These models offer a restricted subset of communication patterns that enable implementation tradeoffs and deliver performance and resource guarantees. This is useful for OpenCL developers operating within the constraints of the FPGA device. We provide a preliminary analysis of our proposal and sketch programmer and compiler responsibilities that would be needed for integrating these features into the FPGA OpenCL environment. © 2017 ACM.

关键词： field programmable gate arrays (FPGA)

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field data analysis of multi spindle lathes for a proven-in-use assessment 27th

Field data analysis of multi spindle lathes for a proven-in-...

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27th European Safety and Reliability conference, ESREL 2017

作者： Nowizki, N. Zeiler, P. Bertsche, B. Mödden, H. Institute of Machine Components University of Stuttgart Germany VDW—German Machine Tool Builders Association Frankfurt Germany

ISBN: (纸本)9781138629370

In this paper, operating data of lathes is analyzed with regard to the specifications of the ISO 13849-1. The Weibull analysis is based on machine running times of 1519 multi spindle automatic lathes. The analyzed safety function, "workpiece clamping" is achieving a maximum performance level b (PL b) for lathes with a standard PLC (programmable logic controller) according to the approach of ISO 13849–1, whereas at least PL c is required. However, in reality, the considered machines are operating for up to thirteen years without any loss of the safety function due to technical failure. The quantitative measure of the performance level is the "average probability of a dangerous failure per hour". Since there is uncertainty regarding the interpretation of this measure, the main possibilities are discussed and a cor-responding parameter is chosen as reference. Since there is no known shape parameter b for the failure of the considered safety function, a parameter study with different shape parameters is carried out. © 2017 Taylor & Francis Group, London.

关键词： C (programming language)

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Vehicular Visible Light Networks with Full Duplex Communications 5

Vehicular Visible Light Networks with Full Duplex Communicat...

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5th IEEE international conference on Models and Technologies for Intelligent Transportation Systems (MT-ITS)

作者： Masini, Barbara M. Bazzi, Alessandro Zanella, Alberto Natl Res Council Italy CNR Inst Elect Comp & Telecommun Engn IEIIT Vle Risorgimento 2 Bologna Italy

ISBN: (纸本)9781509064847

Direct connectivity between vehicles will let a variety of new applications become a reality, from safety to traffic management and infotainment. Different wireless access technologies can enable this kind of connections, from mobile-fi IEEE 802.11p in the US and ETSI G5 in Europe, to the more recent 3GPP long term evolution (LTE) for vehicle-to-vehicle (V2V) communications. To integrate the capabilities and performance of these radio access technologies, light emitting diodes (LEDs) operating in the front and rear vehicles' lights, can introduce a further degree of connectivity through the so called visible light communication (VLC), by setting up direct links between vehicles in visibility and between vehicles and the road side (such as traffic lights and variable message panels). This paper investigates the performance of vehicular visible light networks (VVLNs) in terms of message delivery rate when full-duplex (FD) capabilities are exploited. Specifically, instead of considering carrier sensing multiple access with collision avoidance (CSMA/CA) as foreseen by the IEEE 802.15.7 standard for VLC, we here propose a CSMA with collision detection (CSMA/CD) protocol exploiting the reverse link made available by the concurrent use of LEDs as transmitters and photodiodes as receivers for an immediate feedback during decoding. Results show an increase of up to 10% in the delivered data thanks to FD in realistic urban scenarios and give guidelines to network designers.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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