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检索条件"任意字段=International Conference on Field Programmable Logic and Applications"

共 16769 条记录，以下是4901-4910 订阅

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FuGePeNuNet: Fuzzy Genetic Petri Neural Net: A Knowledge Representation for Fuzzy Expert Systems

FuGePeNuNet: Fuzzy Genetic Petri Neural Net: A Knowledge Rep...

引用

international conference on Fuzzy Theory and Its applications (IFUZZY)

作者： Reddy, Poli Venkata Subba Sri Venkateswara Univ Coll Engn Comp Sci & Engn Tirupati 517502 Andhra Pradesh India

ISBN: (纸本)9781509041114

Knowledge representation is key factor for problem representation particularly for incomplete information in expert systems. Usually incomplete information is fuzzy rather than likelihood. Learning methods are necessary to solve expert problems. The conditional inference method is studied different from Zadeh, Mamdani and TSK methods. Learning fuzzy conditional inference with individual methods fuzzy logic, Genetic algorithms, Petri net and neural net not sufficient for large problems. In this paper FuGePeNuNet method is studded by combining fuzzy logic, Genetic algorithms, Petri net and Neural net for large problems of Fuzzy Expert Systems. The fuzzy medical diagnose is given an example.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Automata-to-Routing: An Open-Source Toolchain for Design-Space Exploration of Spatial Automata Processing Architectures

Automata-to-Routing: An Open-Source Toolchain for Design-Spa...

引用

Annual IEEE Symposium on field-programmable Custom Computing Machines (FCCM)

作者： Jack Wadden Samira Khan Kevin Skadron University of Virginia Charlottesville Virginia

Newly-available spatial architectures to accelerate finite-automata processing have spurred research and development on novel automata-based applications. However, spatial automata processing architecture research is lacking, because of a lack of automata optimization and place-and-route tools. To solve this issue, we propose a new, open-source toolchain-Automata-to-Routing (ATR)-that enables design-space exploration of spatial automata architectures. ATR leverages existing open-source tools for both automata processing and FPGA architecture research. To demonstrate the usefulness of this new toolchain, we use it to analyze design choices of spatial automata processing architectures. We first show that ATR is capable of modeling the logic tiles of a commercially-available spatial automata processing architecture. We then use ATR to compare and contrast two different routing architecture methodologies-hierarchical and 2D-mesh-over a set of diverse automata benchmarks. We show that shallower 2D-mesh-style routing fabrics can route complex automata with equal channel width, while using up to 4.2x fewer logic tile resources.

关键词： Automata Computer architecture Routing Benchmark testing Open source software Tools field programmable gate arrays

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High-Reliable Testing for FPGA Software in Space Utilization Engineering

High-Reliable Testing for FPGA Software in Space Utilization...

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international conference on Dependable Systems and Their applications (DSA)

作者： Tao Zhang Xiaodan Wang Chinese Academy of Sciences Technology and Engineering Center for Space Utilization Beijing P. R. China

Software testing is becoming so challenging work due to large-scale and high performance field programmable Gate Arrays (FPGAs) widely used in space utilization engineering projects. Though there are techniques such as static analysis very popular in industry, no rounded testing framework or testing standard is constructed specifically for FPGA software. Based on traditional testing methods, this paper proposes a novel framework for FPGA testing which supports a through checking on the safety-critical applications. Test coverage is therefore improved by combining technologies including static timing analysis, behavior simulation and board-level testing. Experimental results on control software of Tiangong-2 Project demonstrate the proposed testing framework is valid yet efficient in high-speed signal testing and Triple Modular Redundancy (TMR) design validation.

关键词： Software field programmable gate arrays Timing Analytical models Tunneling magnetoresistance Software testing

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Hybrid System: A Smart Choice for Real Time Application

Hybrid System: A Smart Choice for Real Time Application

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international conference on Computer, Electrical & Communication Engineering (ICCECE)

作者： Saikat Mondal Sudip Kumar Ghorui Roshan Ghosh EE Department Budge Budge Institute of TehnoIogy

Fuzzy logic based control system provides a simple and efficient method to control highly complex and imprecise situation. However, the lack of simple hardware designs that is the capable of implementing fuzzy controller's parameters in a single chip, sometimes limits the capability of fuzzy based system in an automotive and industrial environment. In present days, a reconfigurable hardware platform like field programmable gate array (FPGA) has become an alluring alternative to synthesis and implements the desired system with an appropriate design for automation tool. This paper aims to address different hardware implementation issues of fuzzy system on a real-time environment (FPGA) and also proposes the hardware friendly neuro-fuzzy technique as a better replacement of a fuzzy system. In this paper, a simple rule base has been realized on the Xilinx SPARTAN 3AN FPGA development board to bolster the feasibility and superiority of the neuro-fuzzy over the fuzzy system. For the purpose of hardware implementation, optimum choice in terms of speed, accuracy and resource utilization is obtained in case of neuro-fuzzy technique and the results are in conformation.

关键词： Fuzzy systems field programmable gate arrays Hardware Fuzzy logic Mathematical model Resource management Engines

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Connectivity and Coverage in Machine-Type Communications

Connectivity and Coverage in Machine-Type Communications

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IEEE international conference on Communications (ICC) / Wireless Communications Symposium / 3rd Workshop on Optical Wireless Communications (OWC)

作者： Sarigiannidis, Panagiotis Zygiridis, Theodoros Sarigiannidis, Antonios Lagkas, Thomas D. Obaidat, Mohammad Kantartzis, Nikolaos Univ Western Macedonia Dept Informat & Telecommun Engn Karamanli & Ligeris St Kozani 50100 Greece Democritus Univ Thrace Dept Econ Univ Campus Komotini 69100 Greece Univ Sheffield Int Fac CITY Coll Comp Sci Dept Thessaloniki Greece Fordham Univ Bronx NY 10458 USA Aristotle Univ Thessaloniki Dept Elect & Comp Engn Thessaloniki 54124 Greece

ISBN: (纸本)9781467389990

Machine-type communication (MTC) provides a potential playground for deploying machine-to-machine (M2M), IP-enabled 'things' and wireless sensor networks (WSNs) that support modern, added-value services and applications. 4G/5G technology can facilitate the connectivity and the coverage of the MTC entities and elements by providing M2M-enabled gateways and base stations for carrying traffic streams to/from the backbone network. For example, the latest releases of long-term evolution (LTE) such as LTE-Advanced (LTE-A) are being transformed to support the migration of M2M devices. MTC-oriented technical definitions and requirements are defined to support the emerging M2M proliferation. ETSI describes three types of MTC access methods, namely a) the direct access, b) the gateway access and c) the coordinator access. This work is focused on studying coverage aspects when a gateway access takes place. A deployment planar field is considered where a number of M2M devices are randomly deployed, e.g., a hospital where body sensor networks form a M2M infrastructure. An analytical framework is devised that computes the average number of connected M2M devices when a M2C gateway is randomly placed for supporting connectivity access to the M2M devices. The introduced analytical framework is verified by simulation and numerical results.

关键词： Machine-to-machine communications logic gates Cellular networks Wireless sensor networks Base stations Long Term Evolution

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Improving of a circuit checkability and trustworthiness of data processing results in LUT-based FPGA components of safety-related systems 13

Improving of a circuit checkability and trustworthiness of d...

引用

13th international conference on ICT in Education, Research and Industrial applications. Integration, Harmonization and Knowledge Transfer, ICTERI 2017

作者： Drozd, Oleksandr Drozd, Miroslav Martynyuk, Oleksandr Kuznietsov, Mykola Institute of Computer Systems Odessa National Polytechnic University Ave Shevchenko 1 Odessa65044 Ukraine

The possibility of improving on attributes of a solution which are traditionally opposed each other is proved. For digital components of safety-related systems, the method of improving on attributes of a checkability of the circuit and trustworthiness of the results calculated on FPGA with the LUT-oriented architecture is offered. The method is directed to improving of the ready project by a choice of the version of a program code without change of the hardware decision. Versions of LUT memory programming and a set of faults on which these versions exert impact are generated. Faults of shorts between adjacent address inputs of LUT are considered. Operation of the circuit is simulated on all versions and on all set of faults. The method selects the versions providing increase in a checkability of the circuit in a normal mode and trustworthiness of results in emergency mode of the safety-related systems.

关键词： field programmable gate arrays (FPGA)

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Adaptive Basis Functions for Prototype-based Classification of Functional Data 12

Adaptive Basis Functions for Prototype-based Classification ...

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12th international Workshop on Self-Organizing Maps and Learning Vector Quantization, Clustering and Data Visualization (WSOM)

作者： Bani, Gabriele Seiffert, Udo Biehl, Michael Melchert, Friedrich Univ Modena & Reggio Emilia I-41125 Modena Italy Fraunhofer Inst Factory Operat & Automat Sandtorstr 22 D-39106 Magdeburg Germany Univ Groningen Johann Bernoulli Inst Math & Comp Sci POB 407 NL-9700 AK Groningen Netherlands

ISBN: (纸本)9781509066384

We present a framework for distance-based classification of functional data. We consider the analysis of labeled spectral data and time series by means of Generalized Matrix Relevance Learning Vector Quantization (GMLVQ) as an example. To take advantage of the functional nature a functional expansion of the input data is considered. Instead of using a predefined set of basis functions for the expansion a more flexible scheme of an adaptive functional basis is employed. GMLVQ is applied on the resulting functional parameters to solve the classification task. For comparison of the classification a GMLVQ system is also applied to the raw input data, as well as on data expanded by a different predefined functional basis. Computer experiments show that the methods offers potential to improve classification performance significantly. Furthermore the analysis of the adapted set of basis functions give further insights into the data structure and yields an option for a drastic reduction of dimensionality.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Time-borrowing platform in the Xilinx UltraScale+ family of FPGAs and MPSoCs 26

Time-borrowing platform in the Xilinx UltraScale+ family of ...

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26th international conference on field-programmable logic and applications, FPL 2016

作者： Ganusov, Ilya Devlin, Benjamin Xilinx Inc. 2100 Logic Drive San JoseCA95124-3400 United States

ISBN: (纸本)9782839918442

This paper presents enhancements to the Xilinx UltraScale+ clocking architecture to support fine-grain time-borrowing. Time borrowing improves performance by redistributing timing slack between fast and slow paths. The Ultra-Scale+ architecture introduces programmable hardware delays and pulse generators embedded in the clocking tree to support time-borrowing based both on clock skew scheduling and pulsed latches. This programmable hardware allows borrowing from a few picoseconds to multiple nanoseconds between sequential pipeline stages without any changes to RTL, placement or routing. Vivado algorithms automatically determine when to skew flip-flop clock or convert them to pulsed latches to achieve the highest possible performance. Using the default Vivado flow, this programmable time-borrowing platform delivers 5.5% Fmax increase on average over a suite of 89 industrial designs. It is especially effective on high-speed applications, delivering up to 13.7% Fmax increase on individual designs. We also demonstrate that using non-default features, such as delays cascades or increasing hold margin, can increase average performance gains to 7.4% and 8.5%, respectively. This platform incurs minimum area (less than 0.1% of total chip area) while staying robust in the presence of tight hold constraints and increasing process variation. © 2016 EPFL.

关键词： field programmable gate arrays (FPGA)

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SYCL C++ and OpenCL interoperability experimentation with triSYCL 2017

SYCL C++ and OpenCL interoperability experimentation with tr...

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5th international Workshop on OpenCL, IWOCL 2017

作者： Doumoulakis, Anastasios Keryell, Ronan O'Brien, Kenneth Xilinx Research Labs 2020 Bianconi Avenue DublinD24 T683 Ireland

ISBN: (纸本)9781450352147

Heterogeneous computing is required in systems ranging from low-end embedded systems up to the high-end HPC systems to reach high-performance while keeping power consumption low. Having more and more accelerators and CPUs also creates challenges for the programmer, requiring even more expertise of them. Fortunately, new modern C++-based domain-specific languages, such as the SYCL open standard from Khronos Group, simplify the programming at the full system level while keeping high performance. SYCL is a single-source programming model providing a task graph of heterogeneous kernels that can be run on various accelerators or even just the CPU. The memory heterogeneity is abstracted through buffer objects and the memory usage is abstracted with accessor objects. From these accessors, the task graph is implicitly constructed, the synchronizations and the data movements across the various physical memories are done automatically, by opposition to OpenCL or CUDA. Sometimes, some applications or libraries already exist using the OpenCL standard or some OpenCL kernels are provided, either as OpenCL kernel source code or even as built-in OpenCL kernels written in RTL for extreme optimization on FPGA. SYCL provides an OpenCL interoperability mode to reuse existing OpenCL code while keeping the higher level task graph programming model without needing explicit memory transfers. We present some experiments on two applications on GPU and FPGA with the triSYCL open-source implementation to show the benefits of this OpenCL interoperability mode. © 2017 ACM.

关键词： field programmable gate arrays (FPGA)

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A low bit-width parameter representation method for hardware-oriented convolution neural networks

A low bit-width parameter representation method for hardware...

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international conference on ASIC

作者： Qiang Chen Chen Xin Chenglong Zou Xinan Wang Bo Wang School of ECE The Key Laboratory of Integrated Microsystem Shenzhen China

Convolution neural networks (CNNs) have become the state-of-the-art technique for Artificial Intelligence (AI) applications. But they consume resources heavily both in computation and energy. Compressing the parameters to fewer bits is an effective way to reduce data quantity, making it possible to deploy CNNs on mobile, IoT and other resource-limited devices. The existing means need to re-train the entire networks and tune the parameters. This paper presents a convenient method to compress the parameters of trained CNN models without re-training and fine-tuning. Our method reduces the number of bits from 32 to 5-9 under the same networks and on the same dataset, with the loss of accuracy less than 1%. The logic power of a trained LeNet reduces by 70.58% on FPGA evaluation.

关键词： Quantization (signal) field programmable gate arrays Hardware Adders C++ languages Convolution Neural networks

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