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检索条件"任意字段=International Conference on Field Programmable Logic and Applications"

共 16769 条记录，以下是4941-4950 订阅

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Reconfigurable Implementation of Fuzzy Inference System Using FPGA

Reconfigurable Implementation of Fuzzy Inference System Usin...

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international conference on New Trends in Computing Sciences (ICTCS)

作者： Mehdi Mohammadi Adnan Shaout Department of Electrical and Computer Engineering University of Michigan Dearborn Dearborn Michigan USA

ISBN: (纸本)9781538605288

Hardware implementation of algorithms is always considered to accelerate them. Fuzzy inference system (FIS) is applicable when the mathematical description of a system is inaccessible or system description is complicated and better to be described in linguistic terms. Current hardware implementation approaches requires some extended level of hardware knowledge. In this paper, we investigated current approaches in the field of FPGA-based Fuzzy controllers then a two-input generic FIS module is introduced as a baseline for constructing complicated tree based structure controller. This configurable module is independent of target hardware and needs no information about target architecture. Finally, implementation results show the benefit of this methodology in terms of speed, power, and silicon area.

关键词： Hardware field programmable gate arrays Fuzzy logic Acceleration IP networks Tools Table lookup

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A Hybrid Model Towards Moving Route Prediction Under Data Sparsity 20

A Hybrid Model Towards Moving Route Prediction Under Data Sp...

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20th international conference on Information Fusion (Fusion)

作者： Wang, Liang Wang, Mei Ku, Tao Cheng, Yong Guo, Xinying Xian Univ Sci & Technol Xian 710054 Shaanxi Peoples R China Chinese Acad Sci Shenyang Inst Automat Shenyang 110016 Liaoning Peoples R China Xian Univ Technol Xian 710048 Shaanxi Peoples R China

ISBN: (纸本)9780996452700

Moving route prediction offers important benefits for many emerging location-aware applications such as target advertising and urban traffic management. A common approach to route prediction is to match similar trace recordings from a larger volume of historical trajectories, and return the targeted recorded path as desired answer. However, due to privacy concerns, incentive mechanism and other reasons, especially in small business environment, a limited dataset with sparse trajectories is only available. Actually, the existing sparse dataset cannot cover sufficient query routes, and then the match-based approach may return no results at all. Moreover, the existing sparse dataset may fail many trajectory mining approaches that work well on general environment. In this paper, we investigate moving route prediction from sparse trajectory dataset, and propose a novel hybrid model, namely HMRP, to address the above problem. To avoid sparse distribution over spatial semantic layer, a road network map reconstruction methods are proposed to accommodate the sparse trajectories in semantic transformation. And then, by training historical trajectories, the implicit mobility patterns and Markov transition model are constructed to support route prediction. When a query trajectory arrives, towards its derived potential destination, our proposed HMRP model integrates pattern matching strategy and Markov probability distribution to predict its future route gradually in a complementary way. Experiments on real-life taxicab GPS recorded dataset demonstrate that HMRP method can improve movement prediction precision significantly, comparing with the baseline prediction algorithms. And the response time for each query trajectory is acceptable for most application cases.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Cross Clock Domain Signal Research Based on Dynamic Motivation Model

Cross Clock Domain Signal Research Based on Dynamic Motivati...

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international conference on Dependable Systems and Their applications (DSA)

作者： Shan Zhou Tao Zhang YaWen Yang University of Chinese Academy of Siences Chinese Academy of Sciences Beijing P. R. China

A novel approach is present to process the clock domain crossing (CDC) signals and verify the correctness of function when metastable state happens. In this paper, the classification standard of FPGA internal synchronous and asynchronous clock domain is introduced. Based on the vague thought of clock domain crossing performance, IP mode is used according to different categories. Meanwhile, dynamic motivation model is applied practically. According to the case study, the proposed approach has excellent performance in CDC design and verification.

关键词： Clocks Aerodynamics IP networks Synchronization Standards field programmable gate arrays Aerospace safety

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Domain Decomposition Operation of FDTD/FIT Dedicated Computer for Larger Scale Microwave Simulation 19

Domain Decomposition Operation of FDTD/FIT Dedicated Compute...

引用

19th international conference on Electromagnetics in Advanced applications (ICEAA)

作者： Kawaguchi, H. Muroran Inst Technol Dept Informat & Elect Engn 27-1 Mizumoto Cho Muroran Hokkaido 0908585 Japan

ISBN: (纸本)9781509044511

For High-Performance Computation (HPC) of microwave simulations with potable machines, the dedicated computer of the FDTD/FIT method based on a dataflow architecture has been developed. As one of the most important tasks in the development of the FDTD/FT dataflow machine, this paper discusses an implementation of a domain decomposition method on the FDTD/FIT dedicated computer aiming to large scale simulation by a small size hardware.

关键词： Finite difference methods Time-domain analysis Registers Computational modeling field programmable gate arrays Computer architecture Hardware

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FPGA based hand sign recognition system

FPGA based hand sign recognition system

引用

IEEE international conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)

作者： More Madhura Mahesh Moraes Savio Jerry Dattatray Sujay Bade Wadala Electronics and Telecommunications Engineering Alamuri Ratnamala Institute of Engineering and Technology (ARIET) Maharashtra India Electronics and Telecommunications Engineering Vidyalankar Institute of Technology Mumbai - Maharashtra India

The prehistoric or primitive cave men's where communication first existed or started were using a means of sign language or gesture for communicating with each other. With the dawn of time, the man started working tirelessly to make his life better and better. The inventions of new technologies and the computer brought a huge change in the life of people. The Computer and advent of the internet made communication and transfer of information easier. But this is always an interaction with machines. The future era is conceiving of human-computer interaction (HCI) that can be used for implementing 3D applications in which user can move or rotate his hands without any input devices like keyboard or mouse. The communication involving hand gestures or signs for communication forms a basic platform for the proposed system. Many researchers have performed different work by using different algorithms. Some of them even have revised their previous algorithm. The current work and related literature review have given a way of developing a new system that can overcome all the system and should provide the best accuracy. The proposed system involves capture of images and then processing it, then filtering the unwanted part. The further processing of the image is carried out using FPGA, i.e. field programmable Gate Array. The system desires to give an excellent simulation, good accuracy, minimizes run time and efficiently reduces the power consumption. It will be forming a great alternative with low cost and best computational algorithm. The proposed system is desired to give better results and desired characteristics after implementation.

关键词： field programmable gate arrays Feature extraction Human computer interaction Gesture recognition Very large scale integration logic gates Discrete Fourier transforms

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In vitro development of microvascular networks with a cylindrical fibrin scaffold 12

<i>In vitro</i> development of microvascular networks with a...

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12th IEEE Annual international conference on Nano/Micro Engineered and Molecular Systems (IEEE-NEMS)

作者： Tung, Yen-Ting Wang, Gou-Jen Ju, Jyh-Cherng Natl Chung Hsing Univ PhD Program Tissue Engn & Regenerat Med Taichung 40227 Taiwan Natl Chung Hsing Univ Grad Inst Biomed Engn Taichung 40227 Taiwan Natl Chung Hsing Univ Dept Mech Engn Taichung 40227 Taiwan China Med Univ Grad Inst Basic Med Sci Taichung 40402 Taiwan China Med Univ Hosp Med Res Dept Core Lab Stem Cell Res Taichung Taiwan Natl Chung Hsing Univ Dept Anim Sci Taichung Taiwan Asia Univ Dept Bioinformat & Med Engn Taichung Taiwan

ISBN: (纸本)9781509030590

The importance of generating a microvessel network in vitro lies in the ability to engineer vital tissue of considerable size or working as a platform for biomedical or cardiovascular studies. However, most of the current methods for generating microvessel networks in vitro based on encapsulating the channel structure inside an extracellular matrix like gel, which requires a circulation pumps at the beginning of the culture and increases the difficulties in observing cell situation due to the thickness of the gel. Thus, we propose a biomimetic scaffold-wrapping method which enables fabrication of customized microvascular network in an easier and controllable way. In our previous studies, we had successfully fabricated the cylindrical scaffold with PLGA and confirmed the human umbilical vein endothelial cells (HUVECs) could grow and cover our cylindrical scaffold after seeding on it. However, a relative long-term degradation of PLGA scaffold restricts the scaffold's widely applications. Fibrin, which is a natural fibrous protein and can be degraded with plasmin enzyme at any time, is a more feasible material for fabricating cylindrical scaffolds with controllable degradation. HUVECs were seeded on fibrin scaffolds and cultured without any additional circulation pump. The expression of vascular endothelial marker CD31 and VE-cadherin on scaffold-covering HUVECs indicated that the cultured cells have high possibility to form a functional microvascular network after the treatment of plasmin degradation. Our method allows cells to be cultured on a scaffold using a conventional culture approach and monitors cell conditions continuously. We hope our cell-covered scaffold can serve as a framework for building large tissues or can be used as the core of a vascular chip for in vitro circulation studies.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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THz and microwave properties of 3D-printed nanocarbon based multilayers 19

THz and microwave properties of 3D-printed nanocarbon based ...

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19th international conference on Electromagnetics in Advanced applications (ICEAA)

作者： Kuzhir, P. Paddubskaya, A. Volynets, N. Kotsilkova, R. Ivanov, E. Biro, I. Mark, G. I. Biro, L. P. Maksimenko, S. Belarusian State Univ Inst Nucl Problems Minsk BELARUS Bulgarian Acad Sci Inst Mech Open Lab Expt Micro & Nano Mech Sofia Bulgaria NanoTech Lab Ltd Sofia Bulgaria 3D Wishes Birou Hungary Ctr Energy Res Inst Tech Phys & Mat Sci Ctr Energy Res Budapest Hungary

ISBN: (纸本)9781509044511

We propose a new type of light-weight conductive thin film material having good mechanical properties and electromagnetic shielding efficiency. For that 3D printing through layer-to-layer deposition of nanocarbon containing plastic layers and neat polymer layers was combined with hot pressing to obtain 10 mu m thick films. We show that such composite has Re epsilon = Im epsilon in very broad frequency range, 200GHz - 0.6 THz.

关键词： Three-dimensional displays Pressing programmable logic arrays Mechanical factors Polymers Dielectrics Graphene

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Design and analysis of low power 32 bit full adder using cntfet for dsp applications

Design and analysis of low power 32 bit full adder using cnt...

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international conference on Communication and Computing Systems, ICCCS 2016

作者： Kumar, Vivek Goyal, Priyanka Gautam Buddha University Greater Noida India

ISBN: (纸本)9781138029521

Low power is a changing trend in VLSI, so our main focus is to minimize the power consumption and delay up to a possible extent by implementing 32 bit full adder using CNTFET (Carbon Nano field Effect Transistor) using cadence tool in 180 nm, 90 nm and 45 nm technology. Firstly, 1 bit full adder using above mentioned gates is implemented and afterwards same is done for 32 bit full adder. Various parameters like layout area, power, power product delay and delay were compared with other designs which are already existing like TGA (Transmission Gate adder), CPL (Complementary pass transistor logic), FA_Hybrid, HPSC, TFA (Transmission Full Adder), C-CMOS etc. When CNTFET as strong transmission gates gets coupled with other CNTFET which acts as weak CMOS inverters, we get very efficient value for delay and power consumption as when power supply is 1.8V, at 180 nm technology, the power consumption and delay was recorded very low. Buffers and capacitors are used after every third stage in 32 bit full adder which gives low delay and also low power consumption. Finally, this 32 bit full adder provides better and significant values for power and delay when compared with all other existing circuits for adder which were mentioned above. Also we find this circuit can be used in ALU, microprocessor, and where we need fast computation and calculation due to the very low delay and low power consumption. © 2017 Taylor & Francis Group, London.

关键词： Electric power utilization

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Design of ZigBee-WiFi Gateway Based on MicroBlaze

Design of ZigBee-WiFi Gateway Based on MicroBlaze

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international conference on Computer Technology, Electronics and Communication (ICCTEC)

作者： Hui Li Qiang Miao Dept. Electronic Engineering Dalian Neusoft University of Information Dalian China Dept. Computer Science and Technology Dalian Neusoft University of Information Dalian China

ISBN: (纸本)9781538657850

The paper presents a design of ZigBee-WiFi gateway. The gateway is designed through System on programmable Chip (SOPC). The embedded platform is built through the digital logical gates resources in the field-Programming Gate Array (FPGA) and the bottom software package of developing application programs. The design is implemented with the MicroBlaze embedded soft core processor. The test results show that data forwarding function is normal with the use of ZigBee-WiFi gate and the design has high application promotion value in intelligent home system.

关键词： Wireless fidelity Zigbee logic gates Computer architecture Protocols Hardware Testing

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Computational power analysis of wireless communications systems using operation-level power measurements

Computational power analysis of wireless communications syst...

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international conference on Electrical and Computing Technologies and applications (ICECTA)

作者： M. Tariq A. Al-Dweik B. Mohammad H. Saleh T Stouraitis Department of Electrical and Computer Engineering Khalifa University Abu Dhabi UAE

ISBN: (纸本)9781538608739

This paper presents a novel metric to compare the computational complexity of various digital signal processing (DSP) algorithms used in wireless communications systems. The proposed metric is based on measuring the power consumed by most common mathematical operations, and then, evaluating the total computational power for a given algorithm by considering all mathematical operations performed within that algorithm. Consequently, the widely used computational complexity metric that is computed for each mathematical operation separately is combined into a single metric for the entire algorithm. Therefore, the comparison between different algorithms becomes simpler and more informative. Moreover, the power metric itself is beneficial for practical applications since it can be used to indicate the feasibility of implementing a particular algorithm in field programmable gate array (FPGA) based hardware. The operations considered in this work are addition, subtraction, multiplication and division, all implemented using FPGA for different number of operations and operating frequencies. The obtained results show that the power consumption of such operations is approximately linear as a function of the number of operations and operating frequencies. Moreover, the relative power of the subtraction, multiplication and division with respect to the addition is equal to 1.09, 3.92 and 222.79, respectively. The obtained results are used to evaluate the computational power of several signal processing algorithms in wireless receivers. The obtained results imply that the computational power of several algorithms is prohibitively large for FPGA prototyping.

关键词： Power measurement field programmable gate arrays Frequency measurement Clocks Current measurement Wireless communication Signal processing algorithms

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