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Implementation of Real-Time Object Detection on FPGA 7

Implementation of Real-Time Object Detection on FPGA

引用

7th international conference on Trends in Electronics and Informatics, ICOEI 2023

作者： Rathod, Gayatri Shah, Parin Gajjar, Ruchi Patel, Manish I. Gajjar, Nagendra Institute of Technology Nirma University Electronics and Communication Engineering Department Gujarat Ahmedabad382481 India

ISBN: (纸本)9798350397284

Object detection is a common and challenging problem in today's world. Also due to the rapid development of deep learning employing underlying deep models over the past ten years, many researchers have investigated and contributed to improving the performance of object identification and associated tasks such as object classification, localization, and segmentation. Inference time and detection accuracy are used to rate the effectiveness of any object detector. In terms of detection accuracy, it is observed that the two-stage detectors outperform the single-stage detector however, single-stage detectors outperform their rivals in terms of inference time. Additionally, You Only Look Once (YOLO) and its versions have improved detection accuracy, some-times surpassing two-stage detectors. In this study, we performed a co-design methodology for hardware and software (HW/SW) aimed at Central Processing Unit (CPU) + field programmable Gate Array (FPGA) based heterogeneous platform which is Xilinx FPGA Kria KV260. A CNN-based algorithm is first extended to the YOLOv4, v5L, and v5s framework before being implemented on the Kria KV260, an out-of-the-box platform for developing advanced vision applications. A reduced computation time is observed for the deployment of the Machine Learning model on Kria KV260. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

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Design and Implementation of BIST Architecture for low power VLSI applications using Verilog

Design and Implementation of BIST Architecture for low power...

引用

2023 international conference on Smart Systems for applications in Electrical Sciences, ICSSES 2023

作者： Gonda, Aadesh Bharathi, S.H. Reva University Vlsi and Embedded Systems Bangalore India School of Ece Reva University Bangalore India

ISBN: (纸本)9798350347296

The proposed BIST architecture focuses on minimizing power consumption during the testing phase while maintaining high fault coverage. It leverages the capabilities of the Verilog hardware description language to model and simulate the design. The research investigates various power reduction techniques, including test pattern compression, selective clock gating, and power-aware test scheduling, to optimize power consumption during testing. This research paper presents the design and implementation of a Built-In Self-Test (BIST) architecture specifically tailored for low-power Very Large-Scale Integration (VLSI) applications. The increasing demand for energy-efficient electronic devices and the proliferation of portable systems have necessitated the development of power-aware design techniques. BIST, a onchip testing technique, plays a crucial role in ensuring the quality and reliability of integrated circuits. The implementation is performed on a field-programmable gate array (FPGA) platform, demonstrating the feasibility and practicality of the proposed design. The research contributes to the field of low-power VLSI design by providing a comprehensive BIST architecture that effectively reduces power consumption during testing. The proposed design is compatible with standard Verilog synthesis and is readily applicable to a wide range of low-power VLSI applications. The findings from this study can guide designers in developing energy-efficient and reliable integrated circuits, promoting sustainability, and extending battery life in portable devices. © 2023 IEEE.

关键词： VLSI circuits

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Introduction of high-speed data acquisition system scheme based on FPGA 3

Introduction of high-speed data acquisition system scheme ba...

引用

3rd international conference on Electronic Information Engineering and Data Processing, EIEDP 2024

作者： Lin, Yinghui Xu, Zhijing Sun, Jun Chen, Ren College of Information Engineering Shanghai Maritime University Shanghai China Shanghai Institute of Technical Physics State Key Laboratory of Infrared Physics Key Laboratory of Infrared System Detection and Imaging Technology Chinese Academy of Sciences Shanghai China

ISBN: (纸本)9781510680531

Signal acquisition system is widely used in various fields of reality, due to the data acquisition rate and processor performance enhancement as well as the development of sensor arrays and other technologies, the data acquisition system acquisition and transmission of the signal is exponential growth, in order to solve the high-speed signal acquisition process of the large amount of data, real-time, transmission rate and other issues, the study of high-speed acquisition of signals as well as the transmission program has an important practical significance. FPGA is very suitable to be applied in high-speed signal acquisition system because of its characteristics. In this paper, we firstly introduce the composition of a typical high-speed signal acquisition system based on FPGA, and then briefly introduce the function and development process of each module of the system and introduce the mainstream programs used in several key modules. In engineering applications, different programs should be used in different modules in conjunction with the actual. © 2024 SPIE.

关键词： field programmable gate arrays (FPGA)

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Weather radar emulator based on DDS technology 5

Weather radar emulator based on DDS technology

引用

2023 5th international conference on Information Science, Electrical, and Automation Engineering, ISEAE 2023

作者： Li, Chuhua Li, Yang University of Electronic Science and Technology Chengdu611731 China

ISBN: (纸本)9781510667440

Weather radar simulation technology has many applications in civil aviation, military and other fields. Using the emulator, weather radar signals from the past can be observed repeatedly. With the development of electronic circuit technology, weather radar emulators develop to a faster response speed. This paper introduces a weather radar emulator based on DDS technology and details its design and realization. The test results show that the system can output the waveform specified by the upper computer and drive the upper computer to produce weather radar images. © COPYRIGHT SPIE. Downloading of the abstract is permitted for personal use only.

关键词： field programmable gate arrays (FPGA)

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Model Verification of Resilient Third-Party Monitoring System Against Cyberattacks

Model Verification of Resilient Third-Party Monitoring Syste...

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2022 IEEE international conference on Consumer Electronics, ICCE 2022

作者： Sakata, Kousei Fujita, Shintaro Sawada, Kenji University of Electro-Communications Tokyo Japan

ISBN: (纸本)9781665441544

Industrial control systems (ICS) are required to be designed and operated safely even when subjected to cyberattacks. Fallback control is necessary for the safe operation of ICS. One of fallback control systems is a resilient third-party monitoring system. This system consists of programmable logic Controllers (PLCs) for normal control and for fallback control. The normal PLC controls field devices, and the fallback PLC takes over the control after the normal PLC is attacked. The fallback control of this paper is the control takeover of a robot arm control system. In order to quickly transition to this fallback control, it is necessary to incorporate a supervisor function to manage each PLC function in an integrated manner. This paper aims to propose a modeling method of ICS functions and its analysis method to ensure that the supervisor can work properly under cyberattacks. For modeling, we use UPPAAL and implement the models of each PLC and supervisor on UPPAAL. In order to quantitatively analyze whether the supervisor can really realize the incident response during cyberattacks, we give the specifications necessary for fallback control to the supervisor model using TCTL. © 2022 IEEE.

关键词： programmable logic controllers

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GDI logic Based Design of Decoder Circuit for Low Power applications 7

GDI Logic Based Design of Decoder Circuit for Low Power Appl...

引用

7th IEEE international conference on Computational Systems and Information Technology for Sustainable Solutions, CSITSS 2023

作者： Kaartik, R. Mohapatra, Eleena Rv College of Engineering Electronics and Communication Engineering Bangalore India

ISBN: (纸本)9798350343144

In this paper a novel design of a low power based 3:8 decoder circuit is proposed for high speed operations. Decoders having great application usage in the field of Address Decoding for Memory devices, Control logic for Processors and Controllers, etc., make them an essential part of the design where further power and area reduction can be achieved. The proposed design utilizes the Gate Diffusion Technique (GDI) to recreate the conventional decoder circuit. Cadence Virtuoso tool is used for design of the proposed circuit on 90nm technology. Performance analysis of power, delay and layout area are observed and tabulated for comparison. Overall the proposed design has 60% less power, 55.4% reduced delay & takes 62.% less area when compared to CMOS design decoder circuit. The proposed design can be used to optimize both area and power consumption in various low-power applications such as mobile devices, IoT devices, and other battery-operated systems. © 2023 IEEE.

关键词： Low power electronics

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FPGA Implementation for Multiple CFAR Algorithms

FPGA Implementation for Multiple CFAR Algorithms

引用

2023 international Telecommunications conference, ITC-Egypt 2023

作者： Rihan, Mostafa Y. Nossair, Zaki B. Mubarak, Roaa I. Helwan University Department of Electronics & Communications Engineering Faculty of Engineering Cairo Egypt

ISBN: (纸本)9798350326062

While analyzing radar signals, the constant false alarm rate (CFAR) method is crucial for detecting targets. Target detection has to be very accurate, particularly in nonhomogeneous situations like multi-target or clutter edge conditions. There are several types of CFAR algorithms, which are used in radar applications that need to identify targets in real time. These algorithms require a lot of computational time. In this research, a programmable hardware architecture has been described for the implementation of multiple CFAR algorithms. The implementation will have the ability to swap between several CFAR algorithms: average, max, min, and order statistics. The proposed implementation of CFAR algorithms is tested using adaptive processing of noisy signals for target recognition in real time. Variants of CFAR algorithms are built within one architecture, which is created to handle parallel processing. Xilinx ARTIX 7 FPGA technology is used to develop and map a scalable parallel framework. The Xilinx Vivado toolset's synthesis, post-place and route are to find the best point to linearly speedup processing and resource usage. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

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PLC Based Humidity and Carbon Dioxide Monitoring and Control System for Industries using SCADA Technology 2

PLC Based Humidity and Carbon Dioxide Monitoring and Control...

引用

2nd international conference Computational and Characterization Techniques in Engineering and Sciences, IC3TES 2024

作者： Khaleeq, Musab Bin Kumar Yadav, Akshay Sarfraz, Mohammad Siddiqui, Mohd. Khursheed Shakir, Md. Aligarh Muslim University Zakir Hussain College of Engineering and Technology Aligarh India Integral University Lucknow India Jamia Millia Islamia New Delhi India

ISBN: (纸本)9798350364699

To optimize manufacturing processes and ensure environmental compliance, careful management of humidity and carbon dioxide levels is crucial in industrial contexts. The creation and deployment of a monitoring and control system that measures humidity and CO2 levels accurately using the Vaisala GMW90 sensor is presented in this study. The Allen-Bradley MicroLogix 1400 Series A PLC provides power to the system. PLC manages digital input/output operations. However, for an analog signal, we use an analog input module that is integrated before the PLC, and an analog output module is attached following the PLC to handle continuous analog signals. Analog signals are scaled to guarantee precise control and monitoring. Wonderware's InTouch SCADA software provides real-time monitoring and control since continuous visibility of sensor data is required. By tackling the issues of intermittent data visibility in industrial settings, this technology enables smooth automation and effective environmental control. Because of its enhanced control accuracy, scalability, and adaptability, the suggested solution can be applied to various industrial applications that call for constant ecological monitoring. © 2024 IEEE.

关键词： programmable logic controllers

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Acceleration of Fast Sample Entropy Towards Biomedical applications on FPGAs 21

Acceleration of Fast Sample Entropy Towards Biomedical Appli...

引用

21st international conference on field-programmable Technology (ICFPT)

作者： Chen, Chao da Silva, Bruno Li, Jianqing Liu, Chengyu Southeast Univ Sch Instrument Sci & Engn Nanjing 210096 Peoples R China Vrije Univ Brussel Dept Elect & Informat ETRO B-1050 Brussels Belgium

ISBN: (数字)9781665453363

ISBN: (纸本)9781665453363

Sample Entropy (SampEn) is an information entropy algorithm widely used for complexity analysis and chaos estimation in many applications. In particular, SampEn measures complexity of time series by the conditional probability of the inner pattern. Unfortunately, the straightforward implementation of SampEn is quadratic time complexity, restricting its realtime analysis ability for health applications and long-term data analysis. Although researchers have proposed fast versions of SampEn to avoid unnecessary comparisons, they have not been accelerated yet due to their performance bottleneck in the complex similarity pair process. In this paper, we evaluate fast SampEn algorithms by employing multi-source biomedical signals on an field-programmable Gate Arrays (FPGA). Since fast SampEn algorithms based of a pre-sorting stage promise to outperform other SampEn algorithms, Lightweight SampEn based on Merge Sort is here implemented and optimized. Different type of optimizations, that can be generalized for similar Lightweight-based SampEn algorithms, are used to reduce the overall latency while the data throughput is increased. A load balancing strategy for multi similarity pair modules is also proposed to solve the unbalancing loads, a bottleneck when increasing the execution parallelism of this type of algorithms. As a result, the proposed SampEn architecture runs 10 times faster than the fastest SampEn implementation on a modern CPU.

关键词： Time series analysis Biomedical measurement Throughput Particle measurements Real-time systems Entropy Time measurement

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Development and Implementation of a Control Algorithm for Industrial Pneumatic Sequences

Development and Implementation of a Control Algorithm for In...

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international conference on Autonomous Robots and Agents, ICARA

作者： Sergio Aranda-Egusquiza Department of Electrical and Mechatronics Engineering Universidad de Ingenieria y Tecnologia - UTEC Lima Peru

ISBN: (数字)9798331509231

ISBN: (纸本)9798331509248

Currently, programming sequences for pneumatic industrial processes are carried out using different methods: pneumatic programming (in disuse), electro pneumatic (using electrical contactors) and programming with a PLC (programmable logic Controller). Among these, programming using Ladder logic is the most commonly used and widely recognized for PLC devices. However, its implementation might take large periods of time, becoming a tedious task and increasing its level of complexity as a function of the number of cylinders, movements and phases that the process requires. This work develops and implements a control algorithm in the LabView graphical environment, which is subsequently connected to a Siemens PLC via an NI OPC (National Instruments OLE for Process Control) Server. The control algorithm is experimentally tested and proven successful in various scenarios of industrial pneumatic sequences.

关键词： Service robots Instruments programmable logic devices Process control Programming Pneumatic systems Contactors Servers logic Smart manufacturing

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