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检索条件"任意字段=International Conference on Field Programmable Logic and Applications"

共 16726 条记录，以下是51-60 订阅

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CNTFET Based Pulse Implied Binary Edge Activated Flip-Flop Using Transmission Gate logic for Low Power VLSI applications

CNTFET Based Pulse Implied Binary Edge Activated Flip-Flop U...

引用

2025 international conference on Multi-Agent Systems for Collaborative Intelligence, ICMSCI 2025

作者： Nagarajan, P. Lalith Kumar, S. Hariharan, M. Nitheesh, S. Krishnan, Rahul Bhairavi, R. Srm Institute of Science and Technology Department of Ece Tamilnadu Chennai India

ISBN: (纸本)9798331509828

The rapid evolution of low-power applications in VLSI design calls for innovative transistor technologies that are capable of meeting stringent energy efficiency requirements. Carbon Nanotube field-Effect Transistors (CNTFETs) offer significant advantages over conventional MOSFETs, particularly in nanoscale, low-power, and high-performance circuits. This paper presents a comparative study of two Flip-Flop circuits aimed at power-efficient digital design. The first circuit, an existing design Pass Transistor logic based Implicit Pulsed - Dual Edge Triggered Flip-Flop (PTIP-DETFF) [1] which was originally implemented using MOSFET technology, has been converted into CNTFET technology to facilitate direct performance comparison. The second circuit is a novel CNTFET-based design that employs Pulse Implied Binary Edge Activated Flip-Flop (PI-BEAFF) using Transmission Gate logic, resulting in further optimization of power and delay characteristics. Simulation results reveal that the proposed CNTFET-based flip-flop, designed using 32nm technology, achieves a power reduction of approximately 99.73% and a delay reduction of 41.53%, with an average power of 5.52654 nW and delay of 8.58667 ps, compared to 2.0290 μ W and 14.685 ps in the existing circuit. This analysis considers critical metrics, including Power-Delay-Product (PDP), Energy-Delay-Product (EDP), Power-Energy-Product (PEP), transistor count, and the number of clocked transistors. The results underscore the potential of CNTFET technology in realizing low-power, high-speed digital circuits, highlighting its applicability for future energy-efficient VLSI systems. © 2025 IEEE.

关键词： Flip flop circuits

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FPGA-Implemented Reconfigurable logic Locking Using N-Stage Delays for Obfuscation

FPGA-Implemented Reconfigurable Logic Locking Using N-Stage ...

引用

IEEE Students' conference on Electrical, Electronics and Computer Science (SCEECS)

作者： Saurabh Srivastava Sangeeta Nakhate Dept. of ECE Maulana Azad National Institute of Technology Bhopal India

ISBN: (数字)9798331529833

ISBN: (纸本)9798331529840

System security is becoming an increasingly essential feature of modern computing systems, particularly programmable hardware such as field programmable Gate arrays (FPGA), employed in various applications such as autonomous systems and digital networks. However, safeguarding FPGA-based devices against IP theft and reverse engineering is difficult and a big concern for the semiconductor and defense industries. Previously, various obfuscation approaches such as gate level obfuscation, camouflaging, and strong puff were employed to make a distinct key for every chip. These designs, however, are more area-intensive, consume more power, and are easier to crack the key. In this research, we propose a novel obfuscation idea that integrates a reconfigurable hardware obfuscation block into the original circuit with an additional N-stage Delay circuit to enhance overall system security and resistance to threats. The present idea relates to the increase in the security of the system against the piracy, overbuilding and from the cloning and camouflaging of the chip. The proposed technique does not have any bulky circuit, and it is easily realizable and just requires some additional modules that can easily reconfigured with a very smaller area and power overhead thereby offering performance benefits and increasing the time of sat attack iteration, making the locking system more complex and difficult to decode.

关键词： Resistance Power measurement Defense industry Hardware security Reverse engineering Reconfigurable logic logic gates Delays IP networks field programmable gate arrays

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27th international Symposium on VLSI Design and Test, VDAT 2023

27th International Symposium on VLSI Design and Test, VDAT 2...

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27th international Symposium on VLSI Design and Test, VDAT 2023

ISBN: (纸本)9789819752683

The proceedings contain 27 papers. The special focus in this conference is on VLSI Design and Test. The topics include: A 0.1–4.71 GHz Integer-N CP-PLL-Based Low-Power Frequency Synthesizer for High-Speed applications;A Current-Mode-logic-Based PFD–Charge Pump Circuit for Low-Reference Spur PLLs;an Energy Efficient Mixed logic 2-to-4 Decoder for Embedded Memory applications;Analysis and Modeling of Self-heating and Substrate-Induced Transitions in 5-nm Stacked Nanosheet FET;optimization of Sol–Gel TiO2 Thin Films for Photovoltaic Organic Photodetector;Design and Analysis of Differential Configuration Based Active Inductor for 5G Sub-6 GHz applications;A Low Jitter and High-Speed Flash TDC with PVT Calibration and Its Testing Methodology;a Dual-Mode High-Frequency Grounded Memristor Emulator Circuit;Analysis and Reduction of GOTFET Capacitances Using Physics-Based Compact Modeling;A Fast Transient Low Iq Capless LDO with Protection Circuits;Demonstration of Doped-HfO2 Ferroelectric Based Double Layer Stacked NC FinFET;High-Precision programmable Thermistor Linearization ASIC for Electro-Optical Payload applications;microwave-Assisted Fe3O4-Based Memristor for Brain-Inspired Computing;Current-Sensing ADC with Power Consumption of 57 nW and FoM of 336 fJ/Conversion at 28 nm CMOS Technology;Design and Analysis of Low-Power Protection Circuits for LDO Regulators;Comparative Study of FET Based Biosensors with Metal Oxide Stacked Sensing Membrane;preventing Costly Iterations by Delivering SoC Congestion Aware Standard Cell Lib Using Pin Accessibility Checker;A 0.076-MW 9.8-ENOB 1-MS/s SAR ADC Using Novel R-C Hybrid DAC;Efficient 1-Bit Hybrid Full Adder Design with Low Power Delay Product Using FinFET-TGDI Technology: Simulation and Comparative Study;high Throughput Multiple Device Diagnosis System for Hierarchical Test Designs;Characterization of Multi-Vt Transistors for Analog IC Design in Sub-nanometer Technologies.

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27th international Symposium on VLSI Design and Test, VDAT 2023

27th International Symposium on VLSI Design and Test, VDAT 2...

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27th international Symposium on VLSI Design and Test, VDAT 2023

ISBN: (纸本)9789819737550

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FPGA-Based Adaptive Traffic Management System for Optimizing Five-Point Intersection Flow

FPGA-Based Adaptive Traffic Management System for Optimizing...

引用

international conference on Electronics, Materials Engineering and Nano-Technology (IEMENTech)

作者： Samit Karmakar Supratim Nandi Atalanta Pal Oishi Banerjee Wrishav Das Sumit Barnwal Soumik Kumar Kundu Electronics & Communication Engineering Dept. Institute of Engineering & Management University of Engineering & Management Kolkata India

ISBN: (数字)9798331520762

ISBN: (纸本)9798331520779

The present invention relates to an FPGA driven traffic management system specifically designed for five-point intersections, which are notably complex due to their unique traffic flow patterns. FPGA is field programmable gate of array basically used to implement digital virtual logic into real hardware. Here FPGAs are utilized to process and control this system periodically every 360 sec durations. This innovative approach not only improves traffic flow and reduces waiting times but also contributes to handle emergency like situation and according to that manipulate signals. The adaptability of the invention to diverse traffic conditions makes it a robust solution for urban traffic management challenges.

关键词： Technological innovation Costs VHDL Pedestrians Process control programmable logic arrays logic gates Traffic control Software field programmable gate arrays

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Optimized FPGA Architectures for High-Speed NTT Computation

Optimized FPGA Architectures for High-Speed NTT Computation

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Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT), international conference on

作者： Chetan Harsha Lekkala Sitadevi Bharatula B. Naresh Kumar Reddy K Sarangam Department of ECE Amrita School of Engineering Chennai India

ISBN: (数字)9798350356236

ISBN: (纸本)9798350356243

This research paper aims to enhance the performance of Number Theoretic Transform (NTT) operations in cryptographic applications by leveraging the flexibility and parallel processing capabilities of field programmable Gate Arrays (FPGAs). NTT, integral to many cryptographic algorithms, often faces real-time performance challenges due to computational demands. By implementing NTT on FPGAs, this approach introduces features such as parallelism, pipelining, and dynamic memory management, significantly improving computational efficiency. The proposed architecture, utilizing 8T SRAM on the AMD Kintex 7 FPGA KC705 Kit, optimizes memory bandwidth and polynomial multiplication, resulting in a robust, high-speed implementation suitable for real-time cryptographic tasks. Simu-lation results demonstrate substantial performance gains, offering a valuable framework for future cryptographic hardware designs.

关键词： Random access memory Transforms logic gates Hardware Real-time systems Stability analysis Computational efficiency Cryptography field programmable gate arrays Pipeline processing

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Efficient Algorithm Analysis Of Kidney Images On FPGA

Efficient Algorithm Analysis Of Kidney Images On FPGA

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IEEE Students' conference on Electrical, Electronics and Computer Science (SCEECS)

作者： G.V. Thanuja Ramya S Dept. Electronics and Communication Engineering Manipal Institute of Technology Manipal Academy of Higher Education Manipal Karnataka India

ISBN: (数字)9798331529833

ISBN: (纸本)9798331529840

The field-programmable gate array (FPGA) offers an effective solution to meet the high-performance requirements of real-time digital signal processors. IP cores developed on FPGAs benefit from the programmable logic's flexibility, efficient timing, and adaptability in algorithm modification, coupled with the processing power provided by the embedded processor. Integrating image processing into this sector is an ideal addition, especially in the growing field of edge detection, which is crucial in areas like image pattern recognition, machine learning, and data processing. This paper presents a case study focused on kidney CT scan images for edge detection, utilizing the Sobel and Canny edge detection techniques on the target FPGA device, xc7z020clg484-1. An IP core was designed and generated using VIVADO software, converting image pixels into binary form for pre-processing through these edge detection algorithms. The algorithms were simulated and synthesized on the xc7z020clg484-1 FPGA, with the entire design implemented in Verilog code to create the IP, which connects to the DMA controller throughout the system. This IP core can process multiple CT scan images simultaneously, making it valuable for various biomedical applications. The primary aim of this research is to compare the Sobel and Canny edge detection algorithms to identify the best approach for developing an IP core, evaluated by metrics such as total power consumption, CPU time, execution time, LUT count, and FF usage. The resulting IP core is efficient and conserves resources, making it suitable for other embedded applications.

关键词： Image edge detection Computed tomography Software algorithms Signal processing algorithms Computer architecture Table lookup IP networks logic field programmable gate arrays Kidney

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Improving Error Resilience in FPGA-Based Multi-Level Approximate Multipliers Using Modified Full Adders

Improving Error Resilience in FPGA-Based Multi-Level Approxi...

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Device Intelligence, Computing and Communication Technologies, (DICCT), international conference on

作者： Arunkumar K S Sushma Vangala Siva Teja Department of ECE Saveetha Engineering College Chennai Tamilnadu

ISBN: (数字)9798331543358

ISBN: (纸本)9798331543365

The study provides a novel technique of increasing the tolerance error for FPGAs-dependent multi-level approximate multipliers, in the application of multiplexers along with modified complete adders. Resource usage should be optimized, and circuit simplicity must be improved at last. Although complete adders are critical to the arithmetic operations of digital circuits, the number of adders can increase the amount of power consumed, the amount of space required, and the process time. The proposed design enhances energy efficiency, reduces signal propagation time, and enhances defect tolerance by employing a multiplexer-based adder architecture. The optimized full adder significantly reduces the power consumption up to 27.7%, space utilization up to 22.9%, and gate count up to 22.8% as compared with traditional designs through extensive simulations. The design is suitable for applications that can afford a moderate amount of error as the error rate is less than 5%. This approach provides a long-term, effective, and extensible solution for systems that are constructed using field-programmable gate arrays, all while optimizing power, speed, and dependability for contemporary digital applications.

关键词： Multiplexing Accuracy Computer architecture logic gates Robustness Adders field programmable gate arrays Digital circuits Standards Resilience

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Design and Implementation of LUT Based Approximate Multiplier for Energy-Efficient Computing

Design and Implementation of LUT Based Approximate Multiplie...

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Device Intelligence, Computing and Communication Technologies, (DICCT), international conference on

作者： Silpa Kesav Velagaleti Sujay Malraju Department of ECE CVR College of Engineering Ibrahimpatnam India CVR College of Engineering Ibrahimpatnam India

ISBN: (数字)9798331543358

ISBN: (纸本)9798331543365

A 4×4 approximate multiplier based on LUTs is presented and implemented for digital signal processing applications, with the goal of streamlining energy consumption and improving performance. The proposed multiplier employs Look-Up Tables (LUTs) and carry chain techniques to balance accuracy and hardware efficiency. The design process involves dividing partial products into two LUT-implemented parts, followed by a final combination stage. Simulation results shows that significant improvements over conventional multipliers, with power savings of up to 70% and latency improvements of up to 40%. The proposed design achieves logic power consumption as low as 59 mW while maintaining acceptable accuracy for error-tolerant applications. Consequently, these results validate the proposed multiplier's effectiveness in reducing area usage, lowering power consumption, and increasing speed.

关键词： Power demand Accuracy Simulation Digital signal processing Hardware Table lookup Energy efficient computing logic Optimization field programmable gate arrays

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Leveraging Dual Output LUTs with Pipelining for Efficient BCD to Binary Converter on FPGA

Leveraging Dual Output LUTs with Pipelining for Efficient BC...

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international conference on VLSI Design

作者： Santosh Kumar Ayan Palchaudhuri Department of Electronics & Communication Engineering School of Electrical and Computer Sciences Indian Institute of Technology Bhubaneswar Argul Khordha Odisha India

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

Decimal operands expressed in BCD is often the convenient data format used in embedded systems and human-centric applications. For optimized arithmetic computation on hardware where binary arithmetic can be conveniently processed, input BCD operands should first be converted to binary. This paper explores the versatility of FPGA specific logic primitives, namely the dual output Look-Up Tables (LUTs) and carry chain for efficient realization of parallel and pipelined architectures to optimize throughput and resource utilization for BCD to binary conversion architectures. Primitive instantiation was adopted to ensure design optimization, which involved direct configuration of FPGA logic primitives. The utility ratio of the configured FPGA primitives was increased to extract the best performance. Experimental results demonstrate a good trade-off in speed and area for our proposed architectures when compared with existing designs. We have investigated multiple implementation variants for the addition tree, which serves as a crucial functional logic block in the converter design.

关键词： Embedded systems Computer architecture Very large scale integration Throughput Table lookup logic field programmable gate arrays Adders Optimization Arithmetic

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