This paper investigates the enhancement of True Random Number Generators (TRNGs) in field-programmable Gate Arrays (FPGAs) through programmable Delay logic (PDL). We examine how PDL influences the entropy quality and ...
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ISBN:
(纸本)9798350379068;9798350379051
This paper investigates the enhancement of True Random Number Generators (TRNGs) in field-programmable Gate Arrays (FPGAs) through programmable Delay logic (PDL). We examine how PDL influences the entropy quality and performance of TRNGs by controlling Ring Oscillators (ROs). Our study, conducted using Xilinx Artix-7 7A100T and Kintex Ultrascale KU040 devices, utilizes NIST SP 800-22 tests to evaluate different PDL settings. Findings demonstrate that precise PDL configurations are crucial for optimizing TRNG performance and security. This research underlines the importance of PDL in developing robust FPGA-based security systems, offering significant insights into effective digital system security enhancements.
This research presents a real-time automatic control system for ensuring reliable power supply in distributed generation systems. Leveraging programmablelogic Controllers (PLCs) and Supervisory Control and Data Acqui...
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Bloom filters are a very important tool for many applications including genomics, where they are used as a compact data structure for counting k-mers, represent de Bruijn graphs, and more. Due to their random-access n...
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ISBN:
(纸本)9781665473903
Bloom filters are a very important tool for many applications including genomics, where they are used as a compact data structure for counting k-mers, represent de Bruijn graphs, and more. Due to their random-access nature coupled with the large size required for genomics, Bloom filters for genomics can easily become bound by the random access performance of off-chip memory. This is especially true for accelerators such as FPGAs and GPUs, which can easily remove the computation overhead of the multiple hash functions. As a result, Bloom filter accelerators have typically focused either on small filters which can fit in fast on-chip memory, or require fast off-chip memory fabric such as Hybrid Memory Cubes. In this work, we present BunchBloomer, which improves the cost-effectiveness of FPGA Bloom filter accelerators by making better use of cheaper, lower-power DDR memory. BunchBloomer uses a multi-layer radix sorter to group table updates into bursts directed to the same 8 KiB memory region, which can be efficiently cached in on-chip memory. A single BunchBloomer device outperforms a costly 12-core server by over 2x, demonstrating an order of magnitude better power efficiency. It even achieves better power efficiency compared to published FPGA Bloom filter accelerators equipped with Hybrid Memory Cubes.
This paper explores the applications of Robotic-vision systems controlled by a centralized PLC for Material Handling. This Research project was a part of the advanced programmablelogic controller (PLC) course at Mich...
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ISBN:
(纸本)9798350370058;9798350370164
This paper explores the applications of Robotic-vision systems controlled by a centralized PLC for Material Handling. This Research project was a part of the advanced programmablelogic controller (PLC) course at Michigan Technological University and was performed by setting up communication and integrating PLC with a robot and vision system. PLC acts as a Centralized controller, which gives commands to the Conveyor, Vision system, and Robot. The vision system was taught three model IDs corresponding to the Part Characteristics and the Part Orientation. Proper Material handling is very crucial in any kind of industry, and building an Automatic Material Handling system is a very effective solution to increase efficiency, reduce cost, and increase safety.
In this paper, we present an FPGA design of an extremely low latency scientific machine learning application at the edge. Real-time prediction of errant high-energy particle beams at scientific facilities such as Spal...
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ISBN:
(纸本)9781665473903
In this paper, we present an FPGA design of an extremely low latency scientific machine learning application at the edge. Real-time prediction of errant high-energy particle beams at scientific facilities such as Spallation Neutron Source (SNS) is crucial to avoid damages to the equipment. Machine learning techniques are becoming increasingly effective to detect subtle signatures of the errant beams in the noisy sensor signals. However, to minimize potential damage done by errant beam, real-time errant beam detection has to be completed with extremely low latency, usually less than 1 microsecond. By stream processing the input features and employing out-of-order execution of decision nodes among the decision trees, we demonstrate that our highly efficient FPGA implementation can achieve 60 nanoseconds of computing latency for complex random forest models with 10,000 input features.
We present the NAIL Accelerator Interface Layer (NAIL), a framework for offloading to fieldprogrammable Gate Arrays. NAIL has been optimised for latency-sensitive applications, supporting isolated multi-user accelera...
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ISBN:
(纸本)9798350359114
We present the NAIL Accelerator Interface Layer (NAIL), a framework for offloading to fieldprogrammable Gate Arrays. NAIL has been optimised for latency-sensitive applications, supporting isolated multi-user acceleration. It allows accelerators to be employed through a flexible host communication layer, using asynchronous operation while processing data anywhere in host memory. Multiple independent processors are supported with large numbers of concurrent tasks. NAIL has been deployed at significant scale, and is now released as opensource.
This paper presents a programming language for the design and implementation of reactive embedded applications. The language is compiled to hardware descriptions for reconfiguring field-programmable Gate Arrays (FPGAs...
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This paper mainly focuses on getting acquainted with various applications of programmablelogic Controller (PLC) used in industries. This paper compares and contrasts several research publications and projects on appl...
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Motion target detection plays a crucial role in the field of computer vision, and it is especially important for scenarios that involve real-time monitoring and analysis of dynamic objects, such as systems that monito...
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ISBN:
(纸本)9798400707032
Motion target detection plays a crucial role in the field of computer vision, and it is especially important for scenarios that involve real-time monitoring and analysis of dynamic objects, such as systems that monitor rodent activity in kitchen environments. Given that the kitchen is an important place for food safety, the presence of rodents is likely to lead to serious hygiene and health hazards. Therefore, the adoption of efficient moving target detection techniques can instantly recognize and respond to these problems, ensuring that high hygiene and safety standards are maintained in the kitchen. This study focuses on the design and implementation details of a motion target detection system based on FPGA architecture. FPGA (fieldprogrammablelogic Gate Array), with its powerful parallel processing capability, greatly enhances the processing speed and system response time. The core algorithm of the system adopts the inter-frame difference method, which analyzes the pixel differences between consecutive video frames to identify and track the moving objects. Leveraging the parallel computing advantages of FPGA, the system realizes the fast and accurate positioning of the moving targets and the drawing of bounding boxes, which contributes to a set of highly efficient and robust kitchen rodent monitoring system, greatly enhances the monitoring performance and accuracy, and provides a solid foundation for immediate feedback and hygiene risk management. This provides a solid foundation for immediate feedback and hygiene risk management. In summary, FPGA-based motion target detection technology provides a revolutionary solution for kitchen rodent surveillance, demonstrating its broad applicability and potential in video surveillance and automation applications. Going forward, as the technology evolves and the range of applications expands, we look forward to continuing to optimize system performance to meet even more diverse real-time surveillance needs.
When an application is accelerated with CoarseGrained Reconfigurable Architecture (CGRA), it is compiled into Data Flow Graph (DFG). In conventional CGRA frameworks, only one DFG is accelerated in each epoch. Conseque...
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ISBN:
(纸本)9798350359114
When an application is accelerated with CoarseGrained Reconfigurable Architecture (CGRA), it is compiled into Data Flow Graph (DFG). In conventional CGRA frameworks, only one DFG is accelerated in each epoch. Consequently, singlecontext CGRAs can't fully utilize hardware resources when executing multi-kernel applications. In this paper, we propose a dynamic partial reconfigurable CGRA framework for multikernel applications. The modeled CGRA can flexibly partition hardware resources and support parallelism of multiple DFGs by implementing dynamic partial reconfiguration (DPR). A multikernel scheduler based on integer linear programming (ILP) makes a timetable for the execution state of the application, and an incremental mapper compiles DFGs according to the timetable. Compared with the baseline, TRAM, our framework achieves an average throughput increase of 67.30% and utilization increase of 32.46% for a single task with multikernels while an average execution time reduction of 55.71% and an average utilization increase of 70.43% for applications with multiple tasks.
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