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检索条件"任意字段=International Conference on Field Programmable Logic and Applications"

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Customizable and programmable Deep Learning 27th

Customizable and Programmable Deep Learning

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27th international conference on Pattern Recognition, ICPR 2024

作者： Pal, Ratnabali Kar, Samarjit Sekh, Arif Ahmed National Institute of Technology Durgapur WB Durgapur India Brainware University WB Kolkata India Department of Graphical Systems Vilnius Gediminas Technical University Vilnius Lithuania XIM University Odisha Bhubaneswar India UiT The Arctic University of Norway Tromssa Norway

ISBN: (纸本)9783031781063

In this study, we explore the potential of pre-trained deep learning models, proposing a new approach that emphasizes their reusability and adaptability. Our framework, termed "customizable" deep learning, facilities users to seamlessly integrate diverse pre-trained models for addressing new tasks and enhancing existing solutions. Furthermore, we introduce a "programmable" adapter that enables the flexible combination of different pre-trained modules, expanding the range of applications and customization options. Through empirical experiments, particularly focusing on Visual Question Answering (VQA) for visually impaired (VI) individuals, we demonstrate the practical effectiveness of our methodology. These contributions advance the deep learning field while promoting customization and re-usability across various domains and tasks. The code is available https://***/Ratnabali-Pal/CPDA-VQA. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： Federated learning

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Development and Implementation of a Control Algorithm for Industrial Pneumatic Sequences

Development and Implementation of a Control Algorithm for In...

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international conference on Autonomous Robots and Agents, ICARA

作者： Sergio Aranda-Egusquiza Department of Electrical and Mechatronics Engineering Universidad de Ingenieria y Tecnologia - UTEC Lima Peru

ISBN: (数字)9798331509231

ISBN: (纸本)9798331509248

Currently, programming sequences for pneumatic industrial processes are carried out using different methods: pneumatic programming (in disuse), electro pneumatic (using electrical contactors) and programming with a PLC (programmable logic Controller). Among these, programming using Ladder logic is the most commonly used and widely recognized for PLC devices. However, its implementation might take large periods of time, becoming a tedious task and increasing its level of complexity as a function of the number of cylinders, movements and phases that the process requires. This work develops and implements a control algorithm in the LabView graphical environment, which is subsequently connected to a Siemens PLC via an NI OPC (National Instruments OLE for Process Control) Server. The control algorithm is experimentally tested and proven successful in various scenarios of industrial pneumatic sequences.

关键词： Service robots Instruments programmable logic devices Process control Programming Pneumatic systems Contactors Servers logic Smart manufacturing

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Efficient Co-Approximate Parallel Compressive Depth Reconstruction on FPGA

Efficient Co-Approximate Parallel Compressive Depth Reconstr...

引用

2025 IEEE international conference on Acoustics, Speech, and Signal Processing, ICASSP 2025

作者： Wu, Yun McAllister, John School of Electrical Electronic and Computer Engineering Queen's University Belfast United Kingdom

ISBN: (纸本)9798350368741

Efficient depth image reconstruction from sparse samples is crucial for machine perception applications, such as robotics, vehicle assistance and autonomy. It demands fast processing speed with low power consumption for sensing quality and safety, as well as cost reduction for FPGA and solid state implementations, within constrained resource budgets on edge devices. A new co-approximate framework of parallel approximate compressive depth reconstruction engine on FPGA is proposed using 1 solvers, proximal gradient decent (PGD), with instrumented frequency and voltage scaling during the iterative optimization process. By evaluating various number of parallel approximate processing units for the depth image reconstruction engine, up to 51% further power saving is achieved, and 421× speed up of parallel processing compared to the baseline, henceforth the efficiency is elevated over 43×. © 2025 IEEE.

关键词： Approximate Computing Compressive Sensing Convex Optimization Depth Reconstruction field-programmable Gate Array

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20th EAI international conference on Computer Science and Education in Computer Science, CSECS 2024

20th EAI International Conference on Computer Science and Ed...

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20th EAI international conference on Computer Science and Education in Computer Science, CSECS 2024

ISBN: (纸本)9783031843112

The proceedings contain 23 papers. The special focus in this conference is on Computer Science and Education in Computer Science. The topics include: Enabling Autonomy Through Voice Control: AI-Assisted Mobile Platform;maRz: A Fast, Transparent Fuzzy Machine Learning Technique;segmentation and Data Extraction from Carte du Ciel Astrographic Maps;Quadratic Sets and (3mod5)-Arcs in PG(r,5);the Periodic Table: Chemical Properties and Mendeleev Meets Physical Properties and Machine Learning;large Language Models for Identification of Medical Data in Unstructured Records;impact of the Iteration Length on the Software Quality;double-Stranded Differential Evolution and Particle Swarm Optimization with LibreOffice Nonlinear Programming Solver;analyzing the Geometric Ratios of Greek Vases;assessment of Segmentation Models on Panoramic Radiographic Dental Images;3D Cycle-Consistent Adversarial Network for Designing Dental Implant Crown;Eliminating Risk Involved in Using ChatGPT for Clinical Decision Support System;innovative Approaches for the Mental Development and Education of Children with Autism Through Mixed Reality;applications of Simulation Modeling and Computer Visualizations for Studying Structured Crystals for Implementation in Technical Devices;harnessing programmable logic for Quaternion Multiplication;digital Transformation in Primary and Secondary Education in Bulgaria;building a Chatbot to Adopt an Effective Learning Strategy for Graduate Courses in Computer Science;Impact of the Self-training Over Formative Assessment in SQL Part of University Database Course;teaching and Learning Python by Comparative Visualization;an Interdisciplinary Approach in Education of Master Students in Intelligent Sustainable Habitats;Cross-Continental Insights: Comparative Analysis of Using AI for Information System Stakeholder Analysis in Undergraduate Courses in the EU and USA.

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Design and Performance Analysis of Negative Capacitance Based Junctionless Nanowire FeFET for Memory Cell applications 5th

Design and Performance Analysis of Negative Capacitance Base...

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5th international conference on Electrical and Electronics Engineering, ICEEE 2024

作者： Reddy, B. Vimala Chaudhary, Tarun Singh, Mandeep Nanoelectronics Research Lab Department of Electronic and Communication National Institute of Technology Dr B R Ambedkar Punjab Jalandhar India

ISBN: (纸本)9789819790364

This paper discusses the analysis of Negative Capacitance based junctionless Nanowire FeFET for memory cell applications. The persistent scaling of computer capacity is necessary to handle the data's rapidly rising volume and complexity. Dimensional scalability of field effect transistors (FETs) has reached the boltzmann tyranny limit because of transistors’ inability to handle the power dissipation. The new nanotechnologies have ability to replace the currently used CMOS and other technologies in energy-efficient computer devices. For information systems, negative capacitance based junctionless nanowire ferroelectric FETs are a potential candidate to continue improving power consumption. The NCFeFET analysis is carried out by evaluating drain current, transconductance, energy band, electric field, acceptor concentrations, and electric potential, conduction current density. Due to their energy, area efficiency and combined logic-memory functions, NCFeFETs, at the edge of semiconductor technology, are capable of meeting the requirements of integrated data computer applications. The proposed NCFeFET device has high ON current and small OFF current. The device exhibits a sub-threshold slope of 64.4 mV/dec, and the threshold voltage of 0.477 V. The proposed structure of NCFeFET is designed and simulated using the Silvaco TCAD tool. Proposed NCFeFET devices provides high-density and high-performance circuit applications and would act as a promising candidate for the scientific and research community working in this area. © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2025.

关键词： Nanowires

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Bridging Deep Learning and logic Programming for Explainability through ILP 40

Bridging Deep Learning and Logic Programming for Explainabil...

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40th international conference on logic Programming, ICLP 2024

作者： Dreossi, Talissa University of Udine Udine Italy

My research explores integrating deep learning and logic programming to set the basis for a new generation of AI systems. By combining neural networks with Inductive logic Programming (ILP), the goal is to construct systems that make accurate predictions and generate comprehensible rules to validate these predictions. Deep learning models process and analyze complex data, while ILP techniques derive logical rules to prove the network's conclusions. Explainable AI methods, like eXplainable Answer Set Programming (XASP), elucidate the reasoning behind these rules and decisions. The focus is on applying ILP frameworks, specifically ILASP and FastLAS, to enhance explainability in various domains. My test cases span weather prediction, the legal field, and image recognition. In weather forecasting, the system will predict events and provides explanations using FastLAS, with plans to integrate recurrent neural networks in the future. In the legal domain, the research focuses on interpreting vague decisions and assisting legal professionals by encoding Italian legal articles and learning reasoning patterns from Court of Cassation decisions using ILASP. For biological laboratories, we will collaborate with a research group to automate spermatozoa morphology classification for Bull Breeding Soundness Evaluation using YOLO networks and ILP to explain classification outcomes. This hybrid approach aims to bridge the gap between the high performance of deep learning models and the transparency of symbolic reasoning, advancing AI by providing interpretable and trustworthy applications. © 2025 Open Publishing Association. All rights reserved.

关键词： Weather forecasting

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Low Power Multiplier Using NAND logic Cells

Low Power Multiplier Using NAND Logic Cells

引用

international conference on Electronics, Materials Engineering and Nano-Technology (IEMENTech)

作者： A. K. Tharun B. Chakradhar Reddy M. Vinodhini Department of Electronics and Communication Engineering Amrita School of Engineering Bengaluru Amrita Vishwa Vidyapeetham India

ISBN: (数字)9798331520762

ISBN: (纸本)9798331520779

Different models of multiplier that offer the least power consumption are designed as technology node changes. The motive of the designers is to work on the minimization of power with less penalty in speed and area. The main focus of the present development is on the low power multiplier design for the different applications. This paper proposes a method of an efficient Wallace Tree Multiplier which is power efficient and uses a 7:3 counter consisting of full adders implemented using the NAND logic cells. This proposed design is synthesized in the Cadence Genus tool which uses a 45 nm technology library cell in CMOS. The detailed comparison is performed between two multipliers in which one is designed using 2: 1 multiplexers and Exor gates that already exist and the other using NAND logic cells which is proposed for 4-bit operands. The proposed design of the multiplier which uses NAND logic cells shows that it takes less power and has less delay when it is compared to the multiplier which uses 2: 1 Multiplexers and Exor gates. This design gives a good performance for both FPGA and ASIC platforms.

关键词： Multiplexing Power demand logic gates Minimization Libraries Hardware Delays logic field programmable gate arrays Adders

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Design and Implementation of an Efficient Quantum Cost Optimized Adder Using Reversible logic Gates

Design and Implementation of an Efficient Quantum Cost Optim...

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international conference on Electronics, Materials Engineering and Nano-Technology (IEMENTech)

作者： Shatavisha Dasgupta Sourav Pandey Debjit Roy Agnik Maity Antarik Sinha Mihir Lal Saha dept. of Electronics and Communication Engineering Institute of Engineering & Management Under Univeristy of Engineering & Management kolkata Kolkata India

ISBN: (数字)9798331520762

ISBN: (纸本)9798331520779

In modern Very-Large-Scale Integration (VLSI) technology, managing information loss is a critical challenge. Conventional logic gates, such as AND, OR, and NOT, are prone to data loss during operations, reducing their efficiency for sophisticated applications. Reversible logic gates, which have an equal number of inputs and outputs, offer a solution by preserving data integrity. This paper presents the design and FPGA implementation of an efficient and high-speed full adder circuit utilizing reversible logic gates, namely Feynman, Toffoli, and Peres gates. The design focuses on improving computational efficiency and thermal performance. An analysis of the circuit's quantum cost, garbage outputs, and ancillary inputs reveals its advantages over traditional designs. Proposed design has been realized using Verilog and Synthesize and simulations performed using Xilinx Vivado and Xilinx ISE tools, confirms the functionality and efficiency of the proposed full adder. FPGA implementation of the design has been done using NEXYS A7 (Artix 7 series). The results show that the circuit has a quantum cost of 10, with two garbage outputs and one ancillary input, underscoring its potential for use in low-power, high-performance computing systems and quantum computing applications.

关键词： Performance evaluation Costs Quantum computing Simulation logic gates Very large scale integration Thermal management Hardware design languages Adders field programmable gate arrays

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Hardware-Efficient Polar Decoder for 5G Internet of Things Communication 9th

Hardware-Efficient Polar Decoder for 5G Internet of Things C...

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9th international conference on Intelligent IoT as a Service

作者： Guo, Jing Li, Congduan Sun Yat Sen Univ Sch Elect & Commun Engn Shenzhen Peoples R China

ISBN: (纸本)9783031705069;9783031705076

Polar codes have aroused extensive attention due to their capacity-achieving property and low encoding and decoding complexity. With the increasing demand for real-time and high-quality applications, achieving low-latency communication in resource-constrained scenarios such as on Internet of Things (IoT) devices has become essential. This paper proposes a modified semi-parallel decoder for 5G IoT communication, with low decoding latency and high efficiency of hardware resources. 4-bit decoding algorithm and look-ahead approach are used in this work to reduce latency caused by conventional semi-parallel architecture. For a code length of N = 2(10), the proposed decoder improves latency by 48.64% and 75.19% than the conventional semi-parallel decoder and 2-bit decoder, separately. The significant improvement in hardware utilization rate of processing elements by 68.42% and 119.35% leads to high efficiency of hardware resources.

关键词： Internet of things Polar codes Wireless communication Hardware architecture field programmable gate array

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Efficient FPGA Architecture for DPDK Flow Rules Processing 27

Efficient FPGA Architecture for DPDK Flow Rules Processing

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27th international conference on Advanced Communications Technology, ICACT 2025

作者： Van, Vo Thanh Lam, Nguyen Phu Truong, Nguyen Nhat Phuong, Nguyen Quang Duc, Vu Tuan Toan, Le Ngoc Viettel High Technology Industries Corporation Viettel Group Viet Nam

ISBN: (纸本)9791188428137

With the development of the Internet, the number of connected devices and the amount of transferred data increase annually leading to more complex network applications and limitations in data processing speed. The Data Plane Development Kit (DPDK) addresses these challenges by optimizing packet processing for high-speed network applications, including offloading processing tasks to Network Interface Cards (NICs) hardware using the rte_flow interface, which allows configuration of NICs offloads with specific flow rules. However, with the increasing complexity of network applications, the number of rules used is also growing rapidly, and more complexity. This presents a challenge for building and developing network systems capable of efficiently handling a large number of rules. This paper presents an architecture for processing the rte_flow interface using FPGA-based Smart NICs to leverage the reprogrammable capabilities of hardware accelerators. The architecture uses Ternary Content-Addressable Memory (TCAM) to reduce the key size in the rule tables, significantly increasing the number of rules and rule tables supported by the FPGA. Additionally, a custom DPDK driver (named VTL driver) is developed to manage and implement algorithms aimed at optimizing the number of rules in the hardware. To evaluate our proposed architecture, the Alveo U200 FPGA-based accelerator card is used to implement these features including 8 receive rule tables and 1 transmit rule table per ethernet port. Each table supports up to 2048 wildcard matches and 16384 exact match entries. The system achieves a network throughput of 100 Gbps per port and a rule insert rate of 204 million rules per second. These results significantly enhance hardware acceleration efficiency in networking. Copyright 2025 Global IT Research Institute (GIRI). All rights reserved.

关键词： field programmable gate arrays (FPGA)

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