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检索条件"任意字段=International Conference on Field Programmable Logic and Applications"

共 16726 条记录，以下是71-80 订阅

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A Design of Fault-Tolerant System for Safety-Critical Systems

A Design of Fault-Tolerant System for Safety-Critical System...

引用

international conference on Autonomous Robots and Agents, ICARA

作者： Kai Yoshizawa Nobuyuki Yamasaki Graduate School of Science and Technology Keio University Yokohama Japan

ISBN: (数字)9798331509231

ISBN: (纸本)9798331509248

In safety-critical systems where failures or faults can lead to accidents, especially in special and harsh environments like those encountered in spacecraft, it is well known that multiple levels of errors can significantly increase the likelihood of system failure. For instance, system-level errors may occur due to cable breaks caused by severe vibrations, while gate-level errors can arise from radiation effects on System-on-Chip (SoC) semiconductors. Furthermore, in such specialized environments, human repair is often not feasible, necessitating that the system continue to operate even when a fault occurs in a part of it. Therefore, this research discusses the design, implementation, and evaluation of a redundant system that combines multi-level redundancy mechanisms to tolerate multiple errors and maintain operation. The implementation was carried out on the Space I/O Core (SIOC), a System-on-Chip equipped with processors and I/O for distributed real-time systems. Additionally, bitstreams were created from the implemented logic, and the performance of the fault-tolerant system was evaluated using an actual FPGA.

关键词： Vibrations Space vehicles Redundancy Fault tolerant systems Termination of employment Switches logic gates System-on-chip field programmable gate arrays Robots

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Performance Comparison of 16-Bit ALU and 32-Bit ALU Using Verilog

Performance Comparison of 16-Bit ALU and 32-Bit ALU Using Ve...

引用

Integrated Circuits and Communication Systems (ICICACS), IEEE international conference on

作者： Suganthi Santhanam Rajendra Prasad.S Department of Electronics and Communication Engineering K.Ramakrishnan College of Technology Trichy India Department of Electronics and Communication Engineering Nelliandavar Institute of Technology Ariyalur India

ISBN: (数字)9798331508456

ISBN: (纸本)9798331508463

The increasing demand for efficient and high-performance embedded systems drives the need for optimized Arithmetic and logic Units (ALUs), which are fundamental to their operation. This study aims to address the trade-offs in area, propagation delay, and power consumption, ensuring balanced performance for diverse applications. The study compares the performance of 16-bit and 32-bit ALUs, focusing on key metrics such as area, propagation delay, and power consumption. A trade-off between area and power dissipation is observed, with the 32-bit ALU consuming more power and occupying more area than the 16-bit ALU. To ensure low power consumption, the design activates only one operation and circuit set at a time. The Spartan 6 SP605 FPGA board is utilized to evaluate and compare the performance, with simulations conducted using Verilog and the Xilinx 14.2 software tool. This study presents the design and analysis of a 16-bit Register-Transfer Level (RTL) ALU, showcasing its architectural efficiency with reduced complexity through functional blocks such as adders, subtractors, and logic gates. Synthesis results demonstrate optimized technology schematics using Xilinx-specific components, LUTs and carry logic, ensuring enhanced performance and early issue detection.

关键词： Power demand Embedded systems logic gates Complexity theory logic Hardware design languages field programmable gate arrays Adders Propagation delay Arithmetic

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Fast Bit-Sliced VLSI Architectures on FPGA for Montgomery Domain Modular Inversion

Fast Bit-Sliced VLSI Architectures on FPGA for Montgomery Do...

引用

international conference on VLSI Design

作者： Soham Adhikary Ayan Palchaudhuri Department of Electronics & Communication Engineering School of Electrical and Computer Sciences Indian Institute of Technology Bhubaneswar Argul Khordha Odisha India

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

Modular inversion computation forms a crucial component in Elliptic Curve Cryptosystems. In this paper, we have proposed a fast VLSI architecture for Kaliski's Montgomery domain modular inversion al-gorithm using bit-sliced design paradigm. logic sharing among functional modules and direct configuration of the FPGA logic primitives were adopted to reduce the critical path wherever possible. The hardwired carry chain fabric of FPGA was exploited to bring down the critical path delay. The entire design flow was implemented on modern day FPGA family and the post-implementation timing simulation results are reported.

关键词： Embedded systems Simulation Computer architecture Very large scale integration Elliptic curve cryptography Fabrics Table lookup Delays logic field programmable gate arrays

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Unified Architecture for High-Performance SDR Platforms

Unified Architecture for High-Performance SDR Platforms

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Digital Signal Processing and its applications (DSPA), international conference on

作者： Krutin Denis Ivan Melnik Ivan Varakin Artem Aksenov Institute of Information Technology and Electronics Vladimir State University Vladimir Russia

ISBN: (数字)9798331518752

ISBN: (纸本)9798331518769

The research presents a unified architecture for high-performance software-defined radio (SDR) platforms. The proposed architecture provides flexibility, reconfigurability, and modularity, making it ideal for adapting to the increasing demands of modern communication standards. Utilizing system-on-chip (SoC) and field-programmable gate arrays (FPGAs), this solution streamlines the development and prototyping of specialized radio devices. The results are substantiated by the implementation of next-generation modem prototypes and radio monitoring systems, demonstrating the significant potential of the proposed approach.

关键词： Computer architecture Digital signal processing Modems Mathematical models Libraries field programmable gate arrays Next generation networking Monitoring Software radio Communication standards

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NanoSoftController: A Minimal Soft Processor for System State Control in FPGA Systems 24th

NanoSoftController: A Minimal Soft Processor for System Stat...

引用

24th international conference on Embedded Computer Systems: Architectures, Modeling, and Simulation

作者： Weissbrich, Moritz Seidlitz, Germain Paya-Vaya, Guillermo Tech Univ Carolo Wilhelmina Braunschweig Chair Chip Design Embedded Comp Muhlenpfordtstr 22-23 D-38106 Braunschweig Germany

ISBN: (纸本)9783031783760;9783031783777

In many FPGA-based systems, only sequential system control structures modeled by finite state machines are actually required. In order to deal with complexity, design time, and verification issues, which are weaknesses of traditional hardware description languages, it may be preferred to describe the control flow behaviorally in software. However, it is reported that high-level synthesis for FPGA often generates inferior results in terms of resources and performance when translating software-style control flow description to hardware. In this paper, the NanoSoftController is proposed as an open-source soft processor, which is optimized for minimal and efficient logic resource usage on FPGA platforms. It is targeted at processing sequential finite state machine functionality in software, featuring a compact ISA for control flow in embedded systems and a tiny accumulator-based data path. Furthermore, an efficient mapping of memory to small distributed LUT RAM instances enables its use as a system state machine controller in even very resource-constrained FPGA designs, requiring only 104 slice LUTs and 76 slice registers in total. However, despite all optimizations, in a case study with high-level synthesis results of three reference software-style control applications, i.e., electronic door lock, smart glucose sensor, and sequential sensor network node, a better resource efficiency could not be shown. We evaluate the negative results and provide lessons we learned from them.

关键词： Accumulator architecture FPGA High-level synthesis Microcontroller programmable state machine Soft processor

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Scalable Convolutional Neural Network Inference on-the-Edge using Low-Density FPGAs

Scalable Convolutional Neural Network Inference on-the-Edge ...

引用

Advanced Research in Computing (ICARC), international conference on

作者： Udara Ranabahu S A Suraweera Arachchige W A Susantha Wijesinghe School of Engineering Liverpool John Moores University Liverpool United Kingdom Faculty of Applied Sciences Wayamba University of Sri Lanka Kuliyapitiya Sri Lanka

ISBN: (数字)9798331530983

ISBN: (纸本)9798331530990

Machine learning (ML) inference-based applications are often considered to be computationally expensive and power exhaustive, restricting useful deployment in low-power use cases. To take advantage of ML in power-constrained edge environments, it is critical to reduce the power consumption and increase the overall efficiency, while aiming for performance *** present a characteristics study of a low-powered implementation of ML inference focused on-the-edge, aiming for increased efficiency and predictive cost estimation. A scalable inference accelerator architecture for Convolutional Neural Networks (CNNs) consisting of simple functional blocks was developed at Register-transfer Level (RTL) using Verilog® Hardware Description Language (HDL), and was verified at RTL-level verification using RTL testbenches. The integrated system went through functional verification against a predefined golden model, while being optimized for precision and logic *** accelerator was then converted into a fully-parameterized Reconfigurable FPGA IP with additional purpose-built custom debugging glue logic; and validated on FPGA hardware. The system showed a minimum of 740 times acceleration factor during recorded performance evaluations.

关键词： Maximum likelihood estimation Costs Hardware Silicon Convolutional neural networks IP networks logic Resource management Hardware design languages field programmable gate arrays

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Dynamic Equilibrium in Robotics:Techniques and applications for Self Balancing Robots

Dynamic Equilibrium in Robotics:Techniques and Applications ...

引用

2025 IEEE international Students' conference on Electrical, Electronics and Computer Science, SCEECS 2025

作者： Kumar, Nitin Arora, Ujjawal Chaudhary, Neelu Manav Rachna University Computer Science & Technology Faridabad India

ISBN: (纸本)9798331529833

Self-balancing robots have become a key focus in robotics and control system studies since they are capable of standing on two wheels as an upright system. In the implementation of these systems, PID control, Linear Quadratic Regulation, fuzzy logic as well as reinforcement learning in machine learning is applied to control the balance and motion of the robots in the robots in different environmental conditions. This article reviews literature on self-balanced robots over the last half century moving beyond mechanical and electrical designs to control strategies including how double loop control incorporated PID control and how this has now shifted to machine learning. It also describes sensor fusion techniques where a Kalman filter or complementary role filters is employed sensor's accelerometer data and gyroscope data towards the assistance of estimating how tilted the robot is to the ground in degrees. Practical examples are also analyzed from personal devices such as the Segue, to education and robotics research. The paper also investigates the current challenges in the field including sensor drift , battery life, and especially the need for real time adjustment to varying environmental conditions such as bumpy terrain or perturbations. A number of ways are suggested such as using better sensors, control strategies and low power actuators which all improve balance robot systems. The study finishes with the discussion of the optimal developments, particularly focusing on the use of overcome strategies of controls using artificial intelligence for bringing about more flexibility and independency to self-balancing robots. © 2025 IEEE.

关键词： Three term control systems

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A Unified Hardware Accelerator for Fast Fourier Transform and Number Theoretic Transform

A Unified Hardware Accelerator for Fast Fourier Transform an...

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international conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： Rishabh Shrivastava Chaitanya Prasad Ratnala Durga Manasa Puli Utsav Banerjee Electronic Systems Engineering Indian Institute of Science Bengaluru India

ISBN: (数字)9798350368741

ISBN: (纸本)9798350368758

The Number Theoretic Transform (NTT) is an indispensable tool for computing efficient polynomial multiplications in post-quantum lattice-based cryptography. It has strong resemblance with the Fast Fourier Transform (FFT), which is the most widely used algorithm in digital signal processing. In this work, we demonstrate a unified hardware accelerator supporting both 512-point complex FFT as well as 256-point NTT for the recently standardized NIST post-quantum key encapsulation and digital signature algorithms ML-KEM and MLDSA respectively. Our proposed architecture effectively utilizes the arithmetic circuitry required for complex FFT, and the only additional circuits required are for modular reduction along with modifications in the control logic. Our implementation achieves performance comparable to state-of-the-art ML-KEM / ML-DSA NTT accelerators on FPGA, thus demonstrating how an FFT accelerator can be augmented to support NTT and the unified hardware can be used for both digital signal processing and post-quantum lattice-based cryptography applications.

关键词： Fast Fourier transforms Signal processing algorithms Digital signal processing NIST Polynomials Cryptography logic Speech processing Hardware acceleration field programmable gate arrays

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FPGA-Based 3D EM/MPM Simulation Framework for Medical Image Segmentation applications

FPGA-Based 3D EM/MPM Simulation Framework for Medical Image ...

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international conference on Electronics, Materials Engineering and Nano-Technology (IEMENTech)

作者： Samit Karmakar Arindam Chakraborty Saptarshi Banerjee Ayantika Mondal Satavisha Dutta Sayak Nandi Electronics & Communication Engineering Dept. Institute of Engineering & Management University of Engineering & Management Kolkata India

ISBN: (数字)9798331520762

ISBN: (纸本)9798331520779

Medical image segmentation is a critical process in identifying disease-infected regions for diagnostic and treatment purposes. This paper introduces an FPGA-based framework for implementing the Expectation Maximization/Markov Random field (E M/MP M) algorithm in 3D medical image segmentation. FPGA platforms offer unparalleled advantages in terms of parallel processing, speed, and energy efficiency, making them a promising choice for real-time medical image analysis. This proposed framework enables rapid segmentation of 3D images, leveraging the FPGA's on-chip memory and custom logic for efficient pixel classification and data processing. The adaptive design also supports the integration of external RAM for larger datasets. Simulated using Verilog HDL and Quartus Prime, this work demonstrates accurate segmentation results through virtual testing, thus showcasing the system's robustness for medical applications.

关键词： Image segmentation Three-dimensional displays Random access memory Medical services Parallel processing Real-time systems Energy efficiency Hardware design languages Medical diagnostic imaging field programmable gate arrays

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16 Bit Memory and Power Efficient Truncated Booth Multiplier For High Speed applications/Operations

16 Bit Memory and Power Efficient Truncated Booth Multiplier...

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Mobile Computing and Sustainable Informatics (ICMCSI), international conference on

作者： Yashu Swami T. Senthil Vadivel Department of ECE MRIIRS Faridabad Haryana India Civil Engineering Department MRIIRS Faridabad Haryana India

ISBN: (数字)9798331522667

ISBN: (纸本)9798331522674

We now know that multipliers are a necessary component of all basic circuits. These days, multipliers are the cornerstone of any ALU system. High Radix Booth encoding reduces unfinished product during multiplication, but multipliers also introduce delay and power due to hard multiples. The approximate radix-256 Booth encoding is recommended in order to prevent hard multiples. By shifting and complimenting, a partial encoding method is used to construct partial product pairings. Precise encoding values are determined by adding up matching partial products. For performance testing, a 16x16 bit multiplier with the recommended radix-256 Booth encoding was built. Implementation of a 16-bit Truncated Booth Multiplier on the Nexys 4 DDR FPGA board. and contrast with additional multipliers.

关键词： Memory management Circuits Encoding Delays logic Informatics Mobile computing field programmable gate arrays Testing Arithmetic

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