This paper presents a hydrogel biosensor that can simultaneously sense the co-existence of two substances through mechanical response using aptamer molecular recognition and DNA logic gates. Mechanical response is a p...
详细信息
ISBN:
(纸本)9798350357929
This paper presents a hydrogel biosensor that can simultaneously sense the co-existence of two substances through mechanical response using aptamer molecular recognition and DNA logic gates. Mechanical response is a preferable property in hydrogel sensors, so we have created a swelling hydrogel biosensor and have also added logical processing abilities to widen the applications of the sensor. We demonstrated the biosensor's ability against two targets, caffeine and theophylline, by measuring the swelling ratio of the hydrogel. We believe that our proposed hydrogel biosensor can be applied to many MEMS and mu TAS applications because of its mechanical responsiveness and programmable reactions.
Nothing is perfect. Even carefully developed hardware components can sometimes exhibit unexpected behaviour. This is even more likely in harsh environments, like the one satellites are exposed to. However, on satellit...
详细信息
ISBN:
(纸本)9798350302233
Nothing is perfect. Even carefully developed hardware components can sometimes exhibit unexpected behaviour. This is even more likely in harsh environments, like the one satellites are exposed to. However, on satellites hardware analysis is limited to the data obtained by a constrained set of integrated sensors. Therefore, only expected failure cases can be traced, or only indirect monitoring is possible. In this paper, we present an adaptable way to analyse hardware in the field, to solve this problem. Our approach was implemented in-flight on ESA's OPS-SAT satellite, where such an unexplainable fault was noticed. Fortunately, OPS-SAT contains a reconfigurable field-programmable Gate Array (FPGA) allowing a logic analyser functionality to be implemented. Thereby, any signal present in the FPGA fabric becomes traceable, including all externally connected ones. Here, we describe the implementation, its deployment and the successful execution on the OPS-SAT satellite. Using the captured traces, we performed an in-depth analysis of the erroneous behaviour. Our understanding is, that this is the first time such a technique has been implemented on a flying spacecraft. We hope to encourage in-field adoption, especially in-space FPGA reconfiguration, to drive future innovation.
The Fast Fourier Transform (FFT) is a common signal processing operation used in frequency estimation, a technique that has many applications in a wide range of fields including radar, LiDAR, sonar, medical sciences, ...
详细信息
ISBN:
(纸本)9798350380903;9798350380910
The Fast Fourier Transform (FFT) is a common signal processing operation used in frequency estimation, a technique that has many applications in a wide range of fields including radar, LiDAR, sonar, medical sciences, telecommunications, and metrology. However, in real-time applications, computational intensity often imposes restrictions on frequency resolution, and consequently introducing spectral errors. To address this limitation, the frequency resolution of FFT can be refined for enhanced accuracy by unwrapping the phase information of the frequency component, while maintaining the required FFT points and sampling rate. This paper presents an analysis of diverse windowing techniques, showcasing the potential enhancement of FFT spectral accuracy, particularly for precision-centric measurements. The proposed method is adaptable for deployment in both programmable and non-programmable real-time systems, including Embedded Systems and field-programmable Gate Arrays (FPGAs).
In order to boost the performance of FPGA based resource-constrained embedded Image processing and Machine Learning applications, energy efficient approximate softcore Booth multipliers are designed using Adapative Lo...
详细信息
ISBN:
(纸本)9798350312058
In order to boost the performance of FPGA based resource-constrained embedded Image processing and Machine Learning applications, energy efficient approximate softcore Booth multipliers are designed using Adapative logic modules (ALM) on Intel FPGAs. Two partial products of a multiplier partial product matrix are merged together by addition followed by a Karnaugh map reduction in a unique way. The two merged partial products are then mapped on a single six input ALM, in order to reduce the total resource utilization of the circuit.
logic-gates are key building blocks in digital electronics microelectronic circuits. When printing complex microelectronic circuits, the performance and reliability of printed logic-gates might introduce challenges in...
详细信息
ISBN:
(纸本)9798331529475;9798331529468
logic-gates are key building blocks in digital electronics microelectronic circuits. When printing complex microelectronic circuits, the performance and reliability of printed logic-gates might introduce challenges in designing novel applications. For that reason, we design pass logic-gates, such as AND, OR, and XNOR, based on electrolyte-gated field-effect transistors with indium oxide channel. The presented results demonstrate that printed pass logic-gates significantly reduce the propagation delay time compared to traditional logic-gate designs. In addition, for a number pass logic-gates the transistor count is reduced over traditional logic-gates. Therefore, pass logic-gate designs can in turn enhance the reliability and performance of microelectronic circuits in printed electronics.
In the increased demand for video display of embedded small and medium-sized devices, the design uses a universal asynchronous receiver/transceiver UART for data transmission and VGA for image display through a standa...
详细信息
In this work,our primary focus centered on exploring the adaptability of the dualrate sampling scheme proposed earlier to enhance the performance of multi-degreeof-freedom(multi-DOF)impedance-based haptic *** scheme e...
详细信息
In this work,our primary focus centered on exploring the adaptability of the dualrate sampling scheme proposed earlier to enhance the performance of multi-degreeof-freedom(multi-DOF)impedance-based haptic *** scheme employed independent sampling rates in a haptics controller,effectively mitigating the issue of reduced Z-width at higher sampling rates.A key aspect of our investigation was the intricate implementation of the dual-rate sampling scheme on a fieldprogrammable gate array(FPGA).This implementation on a logic hardware FPGA was challenging and led to the effective comparison of the uniform-rate and dual-rate sampling schemes of the multi-DOF haptic *** used an in-house developed two-DOF pantograph as the haptic interface and an FPGA for implementing the controller ***-based implementation presented challenges that were vital in testing controller performances at higher sampling *** wall experiments were conducted to determine the stable and unstable interactions with the virtual *** complement the experimental results,we simulated the haptics force law for multi-DOF system on Simulink/***,the dual-rate sampling approach maintained the Z-width of the two-DOF haptic interface,even at higher controller sampling rates,distinguishing it from the conventional two-DOF uniform-rate control *** example,employing a dual-rate sampling combination of 20–2 kHz consistently ensured the stable rendering of a maximum virtual stiffness of approximately 700 N/mm and maintained a reliable virtual damping range spanning from 0 to 5 Ns/*** contrast,the 20 kHz uniform-rate sampling approach failed to ensure interface stability in the presence of virtual damping,ultimately resulting in the unsuccessful implementation of any virtual stiffness at higher sampling *** work,therefore,establishes the potential of dual-rate sampling in the realm of haptic technology,with practical applications in multi-DOF systems.
Hardware netlists are generally converted into a bitstream and loaded onto an FPGA board through vendorprovided tools. Due to the proprietary nature of these tools, it is up to the designer to trust the validity of th...
详细信息
ISBN:
(纸本)9798350359114
Hardware netlists are generally converted into a bitstream and loaded onto an FPGA board through vendorprovided tools. Due to the proprietary nature of these tools, it is up to the designer to trust the validity of the design's conversion to bitstream. However, motivated attackers may alter the CAD tools' integrity or manipulate the stored bitstream with the intent to disrupt the functionality of the design. This paper proposes a new method to prove functional equivalence between a synthesized netlist, and the produced FPGA bitstream. The novel approach is comprised of two phases: first, we show how we can utilize implementation information to perform a series of transformations on the netlist, which do not affect its functionality, but ensure it structurally matches what is physically implemented on the FPGA. Second, we present a structural mapping and equivalence checking algorithm that verifies this physical netlist exactly matches the bitstream. We validate this process on several benchmark designs, including checking for false positives by injecting hundreds of design modifications.
The use of a computer-controlled system to monitor and manage various processes household appliances and equipment, such as lights, HVAC systems, security systems, and entertainment systems is known as home automation...
详细信息
System security is becoming an increasingly essential feature of modern computing systems, particularly programmable hardware such as fieldprogrammable Gate arrays (FPGA), employed in various applications such as aut...
详细信息
暂无评论