The proceedings contain 51 papers. The topics discussed include: a dynamic partial reconfigurable CGRA framework for multi-kernel applications;FPGA resource-aware structured pruning for real-time neural networks;stoch...
ISBN:
(纸本)9798350359114
The proceedings contain 51 papers. The topics discussed include: a dynamic partial reconfigurable CGRA framework for multi-kernel applications;FPGA resource-aware structured pruning for real-time neural networks;stochastic implementation of simulated quantum annealing on PYNQ;assuring netlist-to-bitstream equivalence using physical netlist generation and structural comparison;an FPGA-GPU heterogeneous system and implementation for on-board remote sensing data processing;GRAFT: GNN-based adaptive framework for efficient CGRA mapping;AUGER: a multi-objective design space exploration framework for CGRAs;OpenTitan based multi-level security in FPGA system-on-chips;and AEKA: FPGA implementation of area-efficient Karatsuba accelerator for ring-binary-LWE-based lightweight PQC.
The proceedings contain 55 papers. The topics discussed include: fast and flexible FPGA development using hierarchical partial reconfiguration;byteman: a bitstream manipulation framework;ESSPER: elastic and scalable s...
ISBN:
(纸本)9781665453363
The proceedings contain 55 papers. The topics discussed include: fast and flexible FPGA development using hierarchical partial reconfiguration;byteman: a bitstream manipulation framework;ESSPER: elastic and scalable system for high-performance reconfigurable computing with software-bridged APIs;an agile tile-based platform for adaptive heterogeneous many-core systems;application specific instruction-set processors for machine learning applications;quality & generality: a flexible FPGA re-clustering technique to improve packing and placement;a lane detection hardware algorithm based on Helmholtz principle and its application to unmanned mobile vehicles;autonomous driving system with feature extraction using a binarized autoencoder;and a highly customizable and efficient hardware implementation for parallel matrix inversion.
The proceedings contain 51 papers. The topics discussed include: a high-performance and flexible FPGA inference accelerator for decision forests based on prior feature space partitioning;scalable and flexible high-per...
ISBN:
(纸本)9781665420105
The proceedings contain 51 papers. The topics discussed include: a high-performance and flexible FPGA inference accelerator for decision forests based on prior feature space partitioning;scalable and flexible high-performance in-network processing of hash joins in distributed databases;a hexagon-based honeycomb routing architecture for FPGA;an area-efficient multiply-accumulation architecture and implementations for time-domain neural processing;development of autonomous driving system based on image recognition using programmable SoCs;and StreamSVD: low-rank approximation and streaming accelerator co-design.
The proceedings contain 48 papers. The topics discussed include: designing universal logic module FPGA architectures for use with ambipolar transistor technology;a complete open source design flow for Gowin FPGAs;quan...
ISBN:
(纸本)9780738105185
The proceedings contain 48 papers. The topics discussed include: designing universal logic module FPGA architectures for use with ambipolar transistor technology;a complete open source design flow for Gowin FPGAs;quantization-aware dimensionality reduction;a low-cost reconfigurable nonlinear core for embedded DNN applications;bandwidth efficient near-storage accelerator for high-dimensional similarity search;new directions for NewHope: improving performance of post-quantum cryptography through algorithm-level pipelining;performance exploration on pre-implemented CNN hardware accelerator on FPGA;GIB: a novel unidirectional interconnection architecture for FPGA;automatic selection and insertion of HLS directives via a source-to-source compiler;and exploring performance enhancement of event-driven processor networks.
The proceedings contain 81 papers. Topics discussed include: accelerating top-k listnet training for ranking using FPGA;novel neural network applications on new python enabled platforms;tatum: parallel timing analysis...
ISBN:
(纸本)9781728102139
The proceedings contain 81 papers. Topics discussed include: accelerating top-k listnet training for ranking using FPGA;novel neural network applications on new python enabled platforms;tatum: parallel timing analysis for faster design cycles and improved optimization;DP-pack: distributed parallel packing for FPGAs;leflow: automatic compilation of tensorflow machine learning applications to FPGAs;FPGA acceleration of a supervised learning method for hyperspectral image classification;a study on introducing FPGA to ROS based autonomous driving system;real-time object detection and semantic segmentation hardware system with deep learning networks;and dither NN: an accurate neural network with dithering for low bit-precision hardware.
The proceedings contain 54 papers. The topics discussed include: RBSA: range-based simulated annealing for FPGA placement;performance characterization of Altera and Xilinx 28nm FPGAs at cryogenic temperatures;high per...
ISBN:
(纸本)9781538626559
The proceedings contain 54 papers. The topics discussed include: RBSA: range-based simulated annealing for FPGA placement;performance characterization of Altera and Xilinx 28nm FPGAs at cryogenic temperatures;high performance serial ATA Gen3 controllers on FPGA devices;SMEFF: a scalable memory extension fabric for FPGA;AXI over Ethernet;a protocol for the monitoring and control of FPGA clusters;ultra-low latency continuous block-parallel stream windowing using FPGA on-chip memory;HopliteRT: an efficient FPGA NoC for real-time applications;an IP core integration tool-flow for prototyping software-defined radios using static dataflow with access patterns;synthesis of program binaries into FPGA accelerators with runtime dependence validation;pass a pointer: exploring shared virtual memory abstractions in OpenCL tools for FPGAs;toward a new HLS-based methodology for FPGA benchmarking of candidates in cryptographic competitions: the CAESAR contest case study;comparing the cost of protecting selected lightweight block ciphers against differential power analysis in low-cost FPGAs;an energy efficient approach for C4.5 algorithm using OpenCL design flow;an object detector based on multiscale sliding window search using a fully pipelined binarized CNN on an FPGA;lowering dynamic power in stream-based Harris corner detection architecture;and a 42fps full-HD ORB feature extraction accelerator with reduced memory overhead.
The proceedings contain 64 papers. The topics discussed include: high - level synthesis - the right side of history;analysis of transient voltage fluctuations in FPGAs;an energy-efficient near/sub-threshold FPGA inter...
ISBN:
(纸本)9781509056026
The proceedings contain 64 papers. The topics discussed include: high - level synthesis - the right side of history;analysis of transient voltage fluctuations in FPGAs;an energy-efficient near/sub-threshold FPGA interconnect architecture using dynamic voltage scaling and power-gating;network-attached FPGAs for data center applications;automatic code generation of convolutional neural networks in FPGA implementation;random projections for scaling machine learning on FPGAs;high-speed regular expression matching with pipelined automata;enhanced source-level instrumentation for FPGA in-system debug of high-level synthesis designs;a programmable configuration controller for fault-tolerant applications;Eurich C-based high - level synthesis with parallel pattern templates;and rapid design space exploration for soft core processor customization and selection.
The proceedings contain 42 papers. The topics discussed include: an efficient architecture for zero overhead data en-/decryption using reconfigurable cryptographic engine;smart camera for trax playing robot;developmen...
ISBN:
(纸本)9781467390910
The proceedings contain 42 papers. The topics discussed include: an efficient architecture for zero overhead data en-/decryption using reconfigurable cryptographic engine;smart camera for trax playing robot;development of a TRAX artificial intelligence algorithm using path and edge;FPGA Trax solver based on a neural network design;an architecture-algorithm co-design of artificial intelligence for Trax player;an implementation of Trax player using programmable SoC;Trax solver on Zynq with deep Q-network;accelerated cell imaging and classification on FPGAs for quantitative-phase asymmetric-detection time-stretch optical microscopy;leftmost longest regular expression matching in reconfigurable logic;and bringing programmability to the data plane: packet processing with a NoC-enhanced FPGA.
The proceedings contain 70 papers. The topics discussed include: automating customized computing;is high level synthesis ready for business? a computational finance case study;comparing performance, productivity and s...
ISBN:
(纸本)9781479962457
The proceedings contain 70 papers. The topics discussed include: automating customized computing;is high level synthesis ready for business? a computational finance case study;comparing performance, productivity and scalability of the TILT overlay processor to OpenCL HLS;size aware placement for island style FPGAs;analyzing the impact of heterogeneous blocks on FPGA placement quality;low-latency option pricing using systolic binomial trees;collaborative processing of least-square Monte Carlo for American options;accelerating transfer entropy computation;FPGA-accelerated Monte-Carlo integration using stratified sampling and Brownian bridges;time sharing of runtime coarse-grain reconfigurable architectures processing elements in multi-process systems;and architectural synthesis of computational pipelines with decoupled memory access.
暂无评论