The idea of separating the management plane from the data-forwarding gear was first introduced by Software-Defined Networking (SDN), which has brought about a revolutionary new age in networking. This innovation makes...
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Approximate multiplier is a computing unit, which reduces resource and power by sacrificing computational accuracy, and is widely used in fields such as image processing and deep neural networks. In this paper, a low-...
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ISBN:
(数字)9781665453363
ISBN:
(纸本)9781665453363
Approximate multiplier is a computing unit, which reduces resource and power by sacrificing computational accuracy, and is widely used in fields such as image processing and deep neural networks. In this paper, a low-cost 8x8 unsigned approximate multiplier is proposed by considering FPGA architectural features. A stage-aware most significant bits (MSBs) selection scheme is designed for error recovery to trade off accuracy and resource usage. The proposed multiplier saves up to 19.7% LUT utilization while the accuracy only decreases 4%, compared to the accurate Xilinx multiplier IP.
For many years, General Purpose Computing on Graphic Processing Units has been widely exploited in different fields of application. The hardware architectures enabling this kind of computation are increasingly complex...
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ISBN:
(纸本)9798350303209
For many years, General Purpose Computing on Graphic Processing Units has been widely exploited in different fields of application. The hardware architectures enabling this kind of computation are increasingly complex, and their use for on-the-edge applications is often constrained by the limited resources that characterise the systems involved. As such, implementing Graphic Processing Units as soft architectures on fieldprogrammable Gate Arrays could permit to tune their size, performance and resource usage accordingly to the application requirements. Exploiting the so-called Dynamic Partial Reconfiguration technology can allow specialisation of part of the system architecture, creating heterogeneous computing systems with better resource utilisation and lower power consumption. In this work, we describe the implementation on fieldprogrammable Gate Arrays of a System-on-Chip featuring a soft-Graphic Processing Unit, whose size and performance have been tuned by means of Partial Reconfiguration. Considering the Sobel Filter as a reference kernel, we discuss some results for reconfiguration time and throughput. Furthermore, we identify the minimum task sizes for which initiating the reconfiguration process gives an advantage in terms of execution time.
In this paper, a protocol conversion method is proposed for converting the PCI communication bus to the VME communication bus. This proposal includes a detailed description of the FPGA-based PCI bus IP core protocol a...
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Convolutional Neural Networks (CNNs) are increasingly employed for voice recognition, image segmentation, and digit classification. Hardware support techniques are required as the need for processing power rises, and ...
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With the advancement of technology, stereoscopic distance measurement techniques, especially binocular vision technology, have gained significant attention for their high efficiency, low cost, and strong anti-interfer...
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We implemented concatenated KP4-Hamming codes on an FPGA. The different convolutional interleaver structures are proposed and demonstrated. The results show that the best structure can achieved a BER of 3.27e-16 at a ...
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In recent years, there has been a growing demand for multipliers with fast processing speed in fields such as image processing and artificial intelligence. This paper proposes an improved 32-bit multiplier and 48-bit ...
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This paper presents an approach to introduce to the students the concept of the first phase of the compiler-The lexical analysis by developing FPGA based FSMs recognizing different types of lexemes. The aim is to be a...
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NANDFLASH is a mass storage device for the field of aerospace intelligent control. A BCH algorithm-based error correction IP implementation for Zynq-7 platform SOC was proposed in this paper, which can achieve the abi...
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