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检索条件"任意字段=International Conference on Field Programmable Technology"

共 12062 条记录，以下是131-140 订阅

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field programmable Gate Array(FPGA): An Innovation in Hardware technology 2

Field Programmable Gate Array(FPGA): An Innovation in Hardwa...

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2nd international conference for Innovation in technology, INOCON 2023

作者： Farhanaaz Sanju, V. REVA University School of Computer Science and Applications Bangalore India REVA University Department of Computer Science and Enggineering Bangalore India

ISBN: (纸本)9798350320923

FPGA is playing a significant role in the field of computer architecture and design. Other peer technologies of FPGA are embedded microprocessor and microcontroller. In this paper we are comparing the technologies which adapts to network-on-chip architecture. For embedded microprocessor and microcontroller, the hardware is already designed and we write the software instruction by exploiting the hardware. The logic or program developed for the same is purely software. To fetch each instruction, to execute, and to access data from external sources time taken is usually high. The nature of execution is sequential. But in FPGA we write the code to implement the hardware itself using HDL(Hardware Description language). HDL directly implements logic functions and interconnections. Design can be programmed and tested immediately even before fabricating on the chip. The nature of execution in HDL is highly parallel. © 2023 IEEE.

关键词： Microcontrollers

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Towards Evidence-Based Cybersecurity Assessment of programmable Systems to Ensure the Protection of Critical IT Infrastructure 12

Towards Evidence-Based Cybersecurity Assessment of Programma...

引用

12th IEEE international conference on Intelligent Data Acquisition and Advanced Computing Systems: technology and Applications, IDAACS 2023

作者： Illiashenko, Oleg Kharchenko, Vyacheslav Odarushchenko, Oleg National Aerospace University 'KhAI' Department of Computer Systems and Networks Kharkiv61070 Ukraine Institute of Information Science and Technologies 'Alessandro Faedo' - Isti Cnr Software Engineering & Dependable Computing Laboratory Pisa56124 Italy Research and Production Enterprise Rpc Radics Llc Kropyvnytskyi25009 Ukraine

ISBN: (纸本)9798350358056

The paper is devoted to developing scientific principles, methods, means, and information technology of model-oriented verification and evidence-based assessment using functional safety and cybersecurity cases for programmable systems of critical applications (PSCA). In particular, information and control systems important for the safety of nuclear power plants (NPPs), aerospace systems, railway domains, etc., developed using field programmable Gate Arrays (FPGAs) and hardware platforms are reviewed. The goal is to ensure the guaranteed completeness and reliability of its functional safety and cybersecurity assessment by developing and implementing a set of formal and semi-formal methods and tools that consider defects of different nature - physical, design, trojans, and vulnerabilities that can be attacked and lead to a fatal system failure, which results in damaging the critical IT infrastructure. The methods shown are based on integrating algebraic, tabular, graph models, and case assessment methodology. The methods are implemented as appropriate technologies for evidence-based verification and evaluation of PSCA. For formal methods, a prototype of a translator of Very High-Speed Integrated Circuits Hardware Description Language (VHDL) code is developed into an algebra of behaviors. It provides evidence-based verification and a framework and tools to design reports on assessing the cybersecurity and functional safety of programmable systems. © 2023 IEEE.

关键词： critical IT infrastructure cybersecurity FPGA functional safety programmable systems of critical applications

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Resource-Efficient TCAM Implementation Using SRAM 3rd

Resource-Efficient TCAM Implementation Using SRAM

引用

3rd international conference on Micro and Nanoelectronics Devices, Circuits and Systems, MNDCS 2023

作者： Ennampelli, Madhu Varghese, Kuruvilla Department of Electronic Systems Engineering IISc Bangalore India

ISBN: (纸本)9789819944941

Although ternary content-addressable memories (TCAMs) are faster in operation than static random access memories (SRAMs), TCAMs have disadvantages like high power consumption, low bit density, high cost, and complex circuitry. This paper presents a novel approach to adding SRAM advantages to TCAMs using the technique of hybrid partitioning. In hybrid partitioning, the TCAM table is divided both horizontally and vertically. These partitioned blocks are directly mapped to their corresponding SRAM cells. To justify the functionality and performance of the design, a 64â€‰×â€‰32 SRAM-based efficient TCAM is successfully designed on Xilinx field-programmable Gate Array (FPGA) using Verilog HDL. Design parameters were improved in all corners like speed by 10.52%, power by 7.62%, and resource utilization by 50% compared to the best performance reported in literature. And also application-specific integrated circuit (ASIC) of the architecture is designed on the 45-nm CMOS technology node to check the feasibility of design on the chip, and similar to FPGA-based architecture, ASIC implementation performance is also improved. © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2024.

关键词： field programmable gate arrays (FPGA)

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Parallel design and evaluation of GFSR(521, 32) on FPGA

Parallel design and evaluation of GFSR(521, 32) on FPGA

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2022 international conference on Statistics, Data Science, and Computational Intelligence, CSDSCI 2022

作者： Lin, Yun Chen, Qianqian Lin, Ziqi Li, Peilin School of Opto-Electronic and Communication Engineering Xiamen University of Technology Fujian Xiamen361024 China

ISBN: (纸本)9781510661325

GFSR is a common parallel random number generator(RNG). In this paper, the high-performance parallelization of GFSR(521, 32) on field programmable Gate Array (FPGA) is realized by using the hybrid method. The serial and the parallel random number sequence of different numbers are tested using the Diehard test, graphical test and application test. It is found that the random number sequences parallelized by GFSR(521, 32) have good randomness. For 100 million random numbers generated, speedups of 5755× over single-threaded CPU platform and 453× over 32-threaded MIC platform are achieved. Experimental results show that GFSR(521, 32) is a good random number generator suitable for large scale parallel Monte Carlo simulation on FPGA. © 2023 SPIE.

关键词： field programmable gate arrays (FPGA)

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Relay coil-based long-range RFID reader/writer for ISO15693 identification 4

Relay coil-based long-range RFID reader/writer for ISO15693 ...

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4th international conference on Mechanical, Electronics, and Electrical and Automation Control, METMS 2024

作者： Yuan, Xinyu Zhou, Haiyan Chen, Siren Bai, Yurun Wu, Jialing Lu, Liling Chen, Jiayi Institute of Information and Communication Guilin University of Electronic Technology China

ISBN: (数字)9781510679887

ISBN: (纸本)9781510679870

Radio Frequency Identification (RFID) is at the key of Internet of Things development. As RFID technology continues to mature, its application scenarios are expanding, opening a new chapter in the Internet of Things' evolution. Addressing the limitations of current RFID systems, which struggle to simultaneously meet the range and complexity requirements for long-range RFID identification in challenging environments, a system was developed. Through practical experiments, our system can transmit and receive high-frequency signals using RFID antennas at distances of up to 0.9 meters. It is capable of reading information from tags and allows for visual operations through a host computer, effectively meeting real-world production needs. © 2024 SPIE.

关键词： field programmable gate arrays (FPGA)

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Sphinx: A Hybrid Boolean Processor-FPGA Hardware Emulation System 42

Sphinx: A Hybrid Boolean Processor-FPGA Hardware Emulation S...

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42nd IEEE/ACM international conference on Computer-Aided Design (ICCAD)

作者： Pu, Ruiyao Sun, Yiwei Ho, Pei-Hsin Yang, Fan Shang, Li Zeng, Xuan Fudan Univ Sch Microelect State Key Lab Integrated Chips & Syst Shanghai Peoples R China Fudan Univ China & Shanghai Key Lab Data Sci Sch Comp Sci Shanghai Peoples R China UniVista Ind Software Grp Shanghai Peoples R China

ISBN: (纸本)9798350322255

Existing hardware emulators use either FPGA or Boolean processors, which suffer from long compile time and poor debuggability (FPGA-based), or low emulation performance (Boolean processor-based). This work presents Sphinx, a hybrid Boolean processor-FPGA hardware emulation platform aiming to overcome these shortcomings. Sphinx hardware is a new hybrid architecture that integrates software programmable Boolean processors and FPGAs. Sphinx software is a compilation framework that conducts incremental design partitioning and implements the design-under-test components on Boolean processors and the rest on FPGAs. Together, Sphinx enables an incremental emulation flow and demonstrates high emulation performance, fast compile turnarounds, and good debuggability.

关键词： field programmable gate arrays (FPGA)

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FPGA Interfaced IoT System for Smart Medical Robot Monitoring System 2

FPGA Interfaced IoT System for Smart Medical Robot Monitorin...

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2nd international conference on Computer, Communication and Control, IC4 2024

作者： Tharwin Kumar, R. Abinaya, S.P. Prakash, D. Janaki, N. Sivarajan, S. Mani, P. Puducherry Technological University Department of Electrical and Electronics Engineeri Puducherry India Velammal Engineering College Department of Information and Technology Chennai India S. A Engineering College Department of Electronics and Communication Engineering Chennai India Vels Institute of Science Technology and Advanced Studies Department of Electrical and Electronics Engineering Tamilnadu Chennai India Vel Tech Multi Tech Dr. Rangarajan Dr Sakunthala Engineering College Avadi Department of Electrical and Electronic Engineering Chennai India K. Ramakrishnan College of Technology Electronics and Communication Engineering Trichy India

ISBN: (纸本)9798350387933

New and improved technology for illness prevention, early detection, and treatment are being encouraged by rising health consciousness and rising medical care costs. The creation of a low-cost initial verification platform layout depends on the FPGA-based system. It has been suggested in the past that sensor nodes built on the FPGA platform would be entry-level IoT devices. The goal of this paper is to create an IoT-based smart health tracking system. The system was created to use wearable technologies and FPGA to gather health data. This technology employs a robot's sensors as an intelligent sensor interface. A multi-sensor healthcare platform may be coupled with the FPGA-based IoT low-end programmable pulse sensor interface architecture to monitor a person's pulse vital sign. Three sensors the heartbeat sensor, temperature sensor, and blood pressure sensor are employed in this system to collect patient data. It has the ability to constantly track a patient's vital signs. Patients' conditions are communicated to loved ones and medical personnel via SMS and the Blynk website. In an Internet of Things context, the complexity of the code may be minimized by using reconfigurable smart sensor interface with a robot. © 2024 IEEE.

关键词： field programmable gate arrays (FPGA)

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Evaluating Power and Thermal Performance of Ten's Complement on FPGA Board 4

Evaluating Power and Thermal Performance of Ten's Complement...

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4th international conference on Advancement in Electronics and Communication Engineering, AECE 2024

作者： Singh, Gurdeep Mittal, Sonam Chitkara University Chitkara University Institute of Engineering and Technology Punjab India

ISBN: (纸本)9798350364729

Given the increasing demand for energy-efficient digital systems, reducing power consumption in communication circuits is vital in the search for sustainable, green communication. By prioritizing the execution of a particular operation on a Spartan FPGA board, this study overcomes the energy limits in digital circuits. Although the design yields outstanding performance in basic arithmetic operations, the first focus is given to power savings based on the reported 1.656 watts during testing. With a thermal margin of 56°C and no too significant heat generation, good thermal control ensured the system was kept within safe operating parameters. Using just 2.0% of I/O capacity, the design also exhibited effective resource economy. Through hardware performance improvement, this work stresses the capabilities of simple operations like ten's complement to drive energy-efficient design strategies on FPGA systems. © 2024 IEEE.

关键词： field programmable gate arrays (FPGA)

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Optimizing Hardware Resources: A Study on Power, and Temperature in Priority Encoder 5

Optimizing Hardware Resources: A Study on Power, and Tempera...

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5th international conference on Smart Electronics and Communication, ICOSEC 2024

作者： Singh, Gurdeep Kaur, Amanpreet Chitkara University Institute of Engineering and Technology Chitkara University Punjab India

ISBN: (纸本)9798331504403

This study presents a novel method for building an energy-efficient priority encoder-more especially, for FPGA families-that is based on Energy optimization is sometimes disregarded in conventional systems even if it is a fundamental part of encoder designs, particularly in cases of restricted power. Leveraging the unique characteristics of FPGA, optimize topologies to lower power consumption without sacrificing speed or capability using comprehensive synthesis and simulations. This paper validates the efficiency of the approach in generating appreciable power reductions without compromising performance. This discovery not only advances FPGA-based circuit development but also energy savings in many other fields. Among the other factors we have measured are the thermal margin of the Kintex board- 72.7 degrees Celsius-and the board's total power consumed-1.32 W. © 2024 IEEE.

关键词： Energy efficient FPGA (field-programmable Gate Array) Kintex Power saving Priority Encoder Temperature Vivado W (Watt) Xilinx

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A Low-Cost Bit-Serial Hardware Architecture and FPGA implementation of Spiking Neural Network 28

A Low-Cost Bit-Serial Hardware Architecture and FPGA impleme...

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28th international Computer Science and Engineering conference, ICSEC 2024

作者： Thongkham, Thanapol Jewajinda, Yutana Silpakorn University Faculty of Engineering and Industrial Technology Department of Electrical Engineering Nakhon Pathom Thailand

ISBN: (纸本)9798350366860

This paper presents a low-cost bit-serial spiking neural network architecture that employs a binary signed-digit (BSD) number system, which relies on the most significant digit-first (MSD-first) serial addition. A pipeline online bit-serial adder is proposed. The online bit-serial adder performs addition with a limited carry chain and variable length precision. The experiments are conducted using Xilinx Zynq-7000 FPGA. The proposed bit-serial architecture with the adder circuits reduces FPGA resources against bit-parallel implementation. The benefit of the proposed bit-serial architecture is that it allows high throughput computing with scalable precision of the leak-integrate-And-fire (LIF) neural model. The experimental results highlight the suitability of the proposed architecture for deployment in resource-constrained FPGA-based embedded systems. © 2024 IEEE.

关键词： field programmable gate arrays (FPGA)

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