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检索条件"任意字段=International Conference on Field Programmable Technology"

共 12062 条记录，以下是151-160 订阅

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Design of an acoustic direction finding system based on split array frequency domain beamforming algorithm

Design of an acoustic direction finding system based on spli...

引用

2023 international conference on Frontiers of Ocean Science and technology, ICFOST 2023

作者： Gao, Qingze Xia, Shixuan Yu, Fan Dalian Scientific Test & Control Technology Institute Dalian China

According to the technical requirement, the principle of the acoustic direction finding and positioning algorithm is introduced, and based on the engineering implementation requirements of split array frequency domain beam forming algorithm, a hardware implementation method based on FPGA +DSP is introduced, which use FPGA to realize the logic control and two pieces of MS320C6678 multi-core DSP to realize the digital beam forming. The hardware system design scheme can realize the program-controlled amplification, filtering, collection, real-time data storage and beam forming processing of the multi-channel acoustic analog signals for acoustic receiving array. At the same time, it can also communicate with the upper computer to achieve upper computer instructions, data transmission, and parameter settings. It has been verified through engineering practice that this scheme has high data processing efficiency and reliable direction finding calculation effect. © Published under licence by IOP Publishing Ltd.

关键词： field programmable gate arrays (FPGA)

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Hardware Embedded Encryption System based on programmable Cellular Automata 46

Hardware Embedded Encryption System based on Programmable Ce...

引用

46th international Semiconductor conference, CAS 2023

作者： Stanica, George Cosmin Anghelescu, Petre Stanica, Stefan Octavian National University of Science and Technology Politehnica Bucharest University Center Pitesti Romania

ISBN: (纸本)9798350323955

With the ever-increasing need for secure data transmission and storage, encryption systems have become essential in ensuring information confidentiality. This paper proposes an encryption system based on programmable cellular automata (PCA) implemented as hardware embedded solution. The encryption system leverages the inherent parallelism and complex dynamics of cellular automata to provide a robust and customizable encryption mechanism. The design and architecture of the cryptosystem is done by utilizing the field programmable Gate Array (FPGA) board's reconfigurable nature that allows for efficient implementation and optimization of the encryption algorithm in hardware. The effectiveness and viability of the cryptosystem are demonstrated by conducting a comprehensive analysis, including running various simulation scenarios and statistical tests. © 2023 IEEE.

关键词： Cryptography

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An Efficient Clock Gated RSFQ Matrix Multiplier through FPGA Implementation 9

An Efficient Clock Gated RSFQ Matrix Multiplier through FPGA...

引用

9th international conference on Advanced Computing and Communication Systems, ICACCS 2023

作者： Kaarthik, K. Vivek, C. Sivaranjani, S. M. Kumarasamy College of Engineering Karur India Sri Eshwar College of Engineering Coimbatore India

ISBN: (纸本)9798350397376

Multiplier are one of the indispensible component in Arithmetic and Logic Unit. Many applications for image and signal processing use matrix multiplication as their core operation. In order to speed up current solutions and adhere to real-time limitations. The proposed system depicts, the field programmable Gate Array features a clock-gated matrix multiplier. The clock-gating approach is used to impact a large number of bit-slicing multipliers in the suggested multiplier. The major goal of this clock-gating technology is to increase performance and decrease power consumption. This suggested multiplier's output bits be restricted to 16 bits. The fundamental gates like XOR,AND, D-flip flops and complete adders are used to create the multiplier that is being given. The multiplier design that is suggested is put into practise using the Altera Quartus II supporting *** CMOS uses two distinct technologies., such as 65nm and 90nm, are taken into consideration when developing the multiplier. Similar to this, the designing methodologies use two separate FPGA devices, Cyclone and Stratix. By testing the metrics such as delay, area and power, the proposed design is assessed. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

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Parallel CRC On An FPGA At Terabit Speeds 21

Parallel CRC On An FPGA At Terabit Speeds

引用

21st international conference on field-programmable technology, FPT 2022

作者： Clark Shen, Qianfeng Vega, Juan Camilo Chow, Paul University of Toronto Dept. of Electical and Computer Eng. Toronto Canada

ISBN: (数字)9781665453363

ISBN: (纸本)9781665453363

The Cyclic Redundancy Check Algorithm (CRC) is critical for ensuring high data reliability in serial communication such as Ethernet networks, allowing for the detection of corrupted packets with a programmable and arbitrarily small probability of failure. The baseline algorithm, however, is highly serialized due to read after write (RAW) dependencies, preventing efficient parallelization of the algorithm for use in hardware. We built a fully parameterizable open-source IP core that has no such dependencies to produce the equivalent result as the baseline CRC algorithm but in a form that can be fully parallelized, with fully automated pipelining, which works for any CRC polynomial, and with a low-resource end-of-packet alignment. This allows for up to 64-bit CRC to be computed in an FPGA at 4 Tbps. © 2022 IEEE.

关键词： field programmable gate arrays (FPGA)

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Design and Implementation of Target Tracking System Based on High Performance FPGA and DSP 3

Design and Implementation of Target Tracking System Based on...

引用

3rd IEEE international conference on Electronic technology, Communication and Information, ICETCI 2023

作者： Jingying, Hu Jiangsu Automation Research Institute Jiangsu Lianyungang222006 China

ISBN: (纸本)9798350398410

In this paper, a video tracking system based on FPGA+DSP architecture is designed and implemented. The system is based on high performance FPGA and DSP processors, and can achieve real-time video acquisition, preprocessing, target detection and tracking, and output the coordinates of the target in real time. The experiment shows that the system can capture 720*576@30Hz video data in real time through FPGA SERDES interface, and realize real-time target detection and tracking, the computing results are also output in real time through the SERDES interface. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

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Implementation of Neural Network Based Digital Pre-distorter for Power Amplifier Linearisation 2

Implementation of Neural Network Based Digital Pre-distorter...

引用

2nd international conference on Emerging Trends in Information technology and Engineering, ic-ETITE 2024

作者： Bharadwaj, Madiraju Akshay Ramesh, Chinthala Devi, R. V. Sanjika Amrita Vishwa Vidyapeetham Dept. of Electronics and Communication Bangalore India

ISBN: (纸本)9798350328202

Digital pre-distortion refers to the use of digital signal processing to address nonlinearities caused by an analog RF front-end in a wireless transmitter. These nonlinearities can lead to nearby channel interference, reduce the transmitted signal's error vector magnitude, and often require the transmitter to operate at a less efficient but more linear region of the device. This work aims to implement a neural network-based digital predistortion algorithm. This pre-distortion algorithm is modelled using a time-delay kernel ridge regression (KRR) algorithm. This is an advanced machine-learning algorithm that considers memory effects. Both software and hardware platforms have been used for this application to produce effective results and discover a comparative comparison between the performance of software and hardware based on some parameters like accuracy, resource utilization, and operation frequency. The training and testing data of an already existing, simulated model is taken, and hardware implementation for the same is carried out using the Verilog HDL programming using the Xilinx Vivado tool. © 2024 IEEE.

关键词： field programmable gate arrays (FPGA)

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Design of PCIe-Based Color Recognition and Tracking System 7

Design of PCIe-Based Color Recognition and Tracking System

引用

7th IEEE international Electrical and Energy conference, CIEEC 2024

作者： Liu, Changrui Wang, Lingyi Cao, Xinli Sun, Xueting Shang, Yuxin Wuhan Institute of Technology School of Electrical and Information Wuhan China Chinese Institute for Brain Research Beijing China

ISBN: (纸本)9798350359558

The tracking of target location plays an important role in animal behavior experiments. In order to meet the demand for high-speed transmission and fast processing of images in experiments, this paper designs an image transmission and processing system based on PCIe high-speed communication interface, which can track objects of specific colors within the screen in real time. By using the upper computer software designed based on the QT framework, the system is able to receive images containing calibration information in real time and make them available to researchers. The system's control and processing core uses Xilinx's Artix-7 series FPGAs, the Riffa framework to drive the PCIe high-speed communication interface data transceiver, and DDR3 SDRAM as the core of the high-speed memory module. The image acquisition device uses OV7670 CMOS, and the whole system realizes the complete process from image acquisition, processing, transmission to display. © 2024 IEEE.

关键词： field programmable gate arrays (FPGA)

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A Self-powered Neural Stimulator Based on programmable Triboelectric Nanogenerators

A Self-powered Neural Stimulator Based on Programmable Tribo...

引用

45th Annual international conference of the IEEE-Engineering-in-Medicine-and-Biology-Society (EMBC)

作者： Yue, Wenji Yu, Shoujun Guo, Tianruo Wang, Hao Shenzhen Inst Adv Technol 1068 Xueyuan Ave Shenzhen 518055 Peoples R China Univ New South Wales Sydney NSW 2052 Australia

ISBN: (纸本)9798350324471

Modulation of peripheral nerve is an emerging field for neuroprosthesis and bioelectronic medicine. With the developing neural interfacing technology that directly communicates with peripheral nerves, several powering schemes have been investigated for long-term use of implantable devices such as wireless and conversion of human body energy. But due to the limitations such as energy conversion efficiency and complexity, none of these methods can fully replace the current battery-based neuroprosthetic systems. This study proposes a new scheme based on programmable triboelectric nanogenerators for self-powered neural stimulations. The device can generate current pulses of more than 100 V by slightly shaking the device. The capability of neural stimulation is validated by sciatic nerve stimulation. Furthermore, the shaking frequency can control the measured kicking force of the rat leg. This prototype can be further minimized and optimized for a fully implantable self-powered/wireless neuroprosthetic system.

关键词： Nanogenerators

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programmable Logic Array in Quantum Computing 1st

Programmable Logic Array in Quantum Computing

引用

1st international conference on Machine Intelligence and Emerging Technologies, MIET 2022

作者： Akter, Fatema Tabassum, Tamanna Uddin, Mohammed Nasir Computer Science and Engineering Jagannath University Dhaka Bangladesh

ISBN: (纸本)9783031346217

The field of computing known as quantum computing is devoted to creating computer technology that is based on the ideas of quantum theory (which makes sense of the way of behaving of energy and material on the nuclear and subatomic levels). These supercomputers are based on two aspects of quantum physical science: superposition and entanglement. As a result, quantum PCs can handle tasks at speeds that are significantly faster than those of traditional PCs and with a lot less energy consumption. On the other hand, Quantum logic gates are designed to empower this computing field. programmable Logic Array is a type of PLDs (programmable logic devices) and is mainly used for designing combination logic mutually by sequential logic. It could be a general-purpose logic gadget that’s programmable and a client can configure the gadget as a simple logic gate operation to complex systems on a chip. In this work, a PLA is designed using Quantum-based gates. The features of Quantum-based computing help Quantum-based PLA to perform billions of activities simultaneously and can give immense memory in small space. © 2023, ICST Institute for Computer Sciences, Social Informatics and Telecommunications Engineering.

关键词： Logic gates

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High Speed and Low Storage Cost Name Lookup Based on field programmable Gate Array 6

High Speed and Low Storage Cost Name Lookup Based on Field P...

引用

6th international conference on Computer Information Science and Application technology, CISAT 2023

作者： Lu, Jiangtian Li, Tong Diao, Wenlan Beijing Institute of Technology School of Information and Electronics Beijing100081 China

ISBN: (纸本)9781510668546

As a future network architecture, Named Data Networking (NDN) adopts content name addressing. While decoupling content from location and brings about rapid expansion of routing tables, it makes lookup speed a bottleneck for high-speed data forwarding. Compared to the table lookup method involving CPU, FPGA can significantly improve the table lookup speed through parallel processing. However, there is a huge contradiction between the large scale of NDN routing table and the limited memory space on FPGA chips. Using FPGA external memory can store routing tables, but its reading speed is slow. To address the above issues, a novel cuckoo searcher structure was first designed to reduce FPGA storage space consumption, with a capacity of over 500K in 10Mbit storage space, which is at least 4 times higher than existing BCD algorithms. Then, multiple cuckoo searchers were combined in parallel, called Cuc-FIB, to improve the search speed to 312.5M times per second, which is 64% higher than the existing BST algorithm. Cuc-FIB has been deployed on the Xilinx Zynq 7000 FPGA platform, capable of carrying 500K routing tables and completing 10Gbps, 4-port line speed routing forwarding. © 2023 SPIE.

关键词： field programmable gate arrays (FPGA)

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