检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

11,992 篇 会议
70 篇 期刊文献

馆藏范围

12,062 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

5,965 篇 工学
- 4,625 篇 计算机科学与技术...
- 2,163 篇 电子科学与技术（可...
- 2,128 篇 软件工程
- 1,664 篇 电气工程
- 1,112 篇 信息与通信工程
- 842 篇 控制科学与工程
- 447 篇 机械工程
- 445 篇 仪器科学与技术
- 208 篇 动力工程及工程热...
- 185 篇 材料科学与工程（可...
- 177 篇 光学工程
- 163 篇 生物医学工程（可授...
- 154 篇 生物工程
- 113 篇 航空宇航科学与技...
- 101 篇 建筑学
- 79 篇 土木工程
- 75 篇 安全科学与工程
- 69 篇 化学工程与技术
1,560 篇 理学
- 786 篇 数学
- 521 篇 物理学
- 182 篇 系统科学
- 158 篇 生物学
- 112 篇 统计学（可授理学、...
- 81 篇 化学
566 篇 管理学
- 514 篇 管理科学与工程(可...
- 125 篇 工商管理
- 64 篇 图书情报与档案管...
205 篇 医学
- 142 篇 临床医学
- 79 篇 基础医学(可授医学...
77 篇 经济学
- 76 篇 应用经济学
63 篇 法学
48 篇 文学
31 篇 农学
29 篇 教育学
20 篇 军事学
7 篇 艺术学

主题

7,267 篇 field programmab...
3,463 篇 field programmab...
2,298 篇 hardware
1,041 篇 clocks
1,007 篇 computer archite...
512 篇 signal processin...
496 篇 table lookup
420 篇 throughput
419 篇 random access me...
408 篇 algorithm design...
349 篇 logic gates
349 篇 ofdm
345 篇 registers
339 篇 routing
325 篇 hardware design ...
317 篇 modulation
296 篇 estimation
284 篇 switches
268 篇 real-time system...
263 篇 digital signal p...

机构

42 篇 school of inform...
40 篇 department of co...
35 篇 chitkara univers...
30 篇 university of ch...
25 篇 department of el...
24 篇 school of comput...
23 篇 harbin institute...
21 篇 school of engine...
21 篇 beijing institut...
20 篇 institute of vls...
18 篇 graduate school ...
17 篇 fudan univ state...
17 篇 institute of mic...
16 篇 beijing key labo...
16 篇 school of electr...
15 篇 university of sc...
15 篇 school of inform...
14 篇 department of co...
14 篇 school of automa...
13 篇 department of el...

作者

61 篇 wayne luk
37 篇 luk wayne
25 篇 motoki amagasaki
25 篇 masahiro iida
19 篇 minoru watanabe
18 篇 liji wu
18 篇 yu wang
18 篇 gurdeep singh
17 篇 n. masmoudi
16 篇 chao wang
16 篇 amanpreet kaur
15 篇 yang jun
15 篇 suhaib a. fahmy
15 篇 wang lingli
14 篇 iouliia skliarov...
14 篇 george a. consta...
14 篇 valery sklyarov
14 篇 saniie jafar
13 篇 wang lei
13 篇 paul chow

语言

11,861 篇 英文
124 篇 中文
76 篇 其他
1 篇 俄文

检索条件"任意字段=International Conference on Field Programmable Technology"

共 12062 条记录，以下是11-20 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Introducing the NAIL Accelerator Interface Layer for Low Latency FPGA Offload 22

Introducing the NAIL Accelerator Interface Layer for Low Lat...

引用

22nd international conference on field programmable technology (ICFPT)

作者： Grindley, Edward Gray, Thurstan Wilkinson, James Vaux, Chris Ardron, Adam Deeley, Jack Elliott, Alexander Sumithran, Nidhin Thandassery Fahmy, Suhaib A. Alan Turing Inst London England Univ Warwick Sch Engn Coventry W Midlands England

ISBN: (纸本)9798350359114

We present the NAIL Accelerator Interface Layer (NAIL), a framework for offloading to field programmable Gate Arrays. NAIL has been optimised for latency-sensitive applications, supporting isolated multi-user acceleration. It allows accelerators to be employed through a flexible host communication layer, using asynchronous operation while processing data anywhere in host memory. Multiple independent processors are supported with large numbers of concurrent tasks. NAIL has been deployed at significant scale, and is now released as opensource.

关键词： field programmable gate arrays Virtualization

来源：评论

学校读者我要写书评

暂无评论

Traffic Flow Optimization using a Chaotic Boltzmann Machine Annealer on an FPGA 22

Traffic Flow Optimization using a Chaotic Boltzmann Machine ...

引用

22nd international conference on field programmable technology (ICFPT)

作者： Yoshioka, Kanta Tanaka, Yuichiro Tamukoh, Hakaru Kyushu Inst Technol Grad Sch Life Sci & Syst Engn Kitakyushu Fukuoka Japan Kyushu Inst Technol Res Ctr Neuromorph AI Hardware Kitakyushu Fukuoka Japan

ISBN: (纸本)9798350359114

We demonstrate a chaotic Boltzmann machine annealer, which is a field-programmable gate array (FPGA)-based high-performance annealing machine, and a control system powered by two open-source software packages. The annealer is employed in solving a large-scale real-world optimization problem, the traffic flow optimization. This involves distributing 500 car routes between the Haneda Airport area to the Pacifico Yokohama area, the venue of the international conference on field programmable technology 2023, while minimizing the total driving distance and preventing traffic jams. We obtain solutions that are comparable in accuracy to solutions of simulated annealing running on a graphics processing unit (GPU-SA) and a central processing unit (CPU-SA). The annealing machine on an FPGA is approximately 571 and 97600 times as fast as the GPUSA and the CPU-SA, respectively. We will demonstrate solving traffic flow optimization in the towns familiar to the visitors.

关键词： neural networks Ising machine annealing machine field-programmable gate array

来源：评论

学校读者我要写书评

暂无评论

PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inference 22

PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latenc...

引用

22nd international conference on field programmable technology (ICFPT)

作者： Andronic, Marta Constantinides, George A. Imperial Coll London Dept Elect & Elect Engn London England

ISBN: (纸本)9798350359114

field-programmable gate arrays (FPGAs) are widely used to implement deep learning inference. Standard deep neural network inference involves the computation of interleaved linear maps and nonlinear activation functions. Prior work for ultra-low latency implementations has hardcoded the combination of linear maps and nonlinear activations inside FPGA lookup tables (LUTs). Our work is motivated by the idea that the LUTs in an FPGA can be used to implement a much greater variety of functions than this. In this paper, we propose a novel approach to training neural networks for FPGA deployment using multivariate polynomials as the basic building block. Our method takes advantage of the flexibility offered by the soft logic, hiding the polynomial evaluation inside the LUTs with minimal overhead. We show that by using polynomial building blocks, we can achieve the same accuracy using considerably fewer layers of soft logic than by using linear functions, leading to significant latency and area improvements. We demonstrate the effectiveness of this approach in three tasks: network intrusion detection, jet identification at the CERN Large Hadron Collider, and handwritten digit recognition using the MNIST dataset.

关键词： deep learning inference field-programmable gate array hardware accelerator LUT-based neural networks soft logic

来源：评论

学校读者我要写书评

暂无评论

DSLUT: An Asymmetric LUT and its Automatic Design Flow Based on Practical Functions 22

DSLUT: An Asymmetric LUT and its Automatic Design Flow Based...

引用

22nd international conference on field programmable technology (ICFPT)

作者： Yang, Moucheng Zhu, Kaixiang Wang, Lingli Zhou, Xuegong Fudan Univ State Key Lab ASIC & Syst Shanghai Peoples R China Fudan Univ Inst Big Data Shanghai Peoples R China

ISBN: (纸本)9798350359114

The conventional LUT is redundant since practical functions in real-world benchmarks only occupy a small proportion of all the functions. For example, there are only 3881 out of more than 1014 NPN classes of 6-input functions occurring in the mapped netlists of the VTR8 and Koios benchmarks. Therefore, we propose a novel LUT-like architecture, named DSLUT, with asymmetric inputs and programmable bits to efficiently implement the practical functions in domain-specific benchmarks instead of all the functions. The compact structure of the MUX Tree in the conventional LUT is preserved, while fewer programmable bits are connected to the MUX Tree according to the bit assignment. A 6-input DSLUT with 26 SRAM bits is generated for evaluation, which is based on the practical functions of 39 circuits from the VTR8 and Koios benchmarks. After the synthesis flow of ABC, the post-synthesis results show that the proposed DSLUT6 architecture reduces the number of levels by 10.98% at a cost of 7.25% area overhead compared to LUT5 architecture, while LUT6 reduces 15.16% levels at a cost of 51.73% more PLB area.

关键词： EDA FPGA Architecture programmable Logic Block

来源：评论

学校读者我要写书评

暂无评论

Accelerating the ATDCA Algorithm for Endmember Extraction from Hyperspectral Imagery with Intel oneAPI for FPGAs 33

Accelerating the ATDCA Algorithm for Endmember Extraction fr...

引用

33rd international conference on field-programmable Logic and Applications (FPL)

作者： Macias, Ruben Bernabe, Sergio Gonzalez, Carlos Univ Complutense Madrid E-28040 Madrid Spain

ISBN: (纸本)9798350341515

The decomposition of the observed pixel spectrum of hyperspectral data into its constituent spectral signatures (or endmembers) and a set of corresponding fractional abundances is known as hyperspectral unmixing. To carry out this analysis, it is required to use a computational technology with high-performance computing due to the high dimensionality of the data and the high complexity of the unmixing algorithms. field programmable Gate Arrays (FPGAs) are excellently suited to processing needs since they provide flexibility, low power consumption, and great performance. Faster alternative development methods are needed because the rate at which new algorithms for hyperspectral analysis are developed is substantially higher than the rate at which these algorithms are implemented on FPGAs. High-level synthesis (HLS) is a technology that assists with the transformation of a behavioral description of hardware into a register transfer level (RTL) model, thus reducing development times. In this work, the automatic target classification and detection algorithm (ATDCA) has been accelerated on FPGAs using Dataparalell C++ (DPC++) and Intel oneAPI. The analysis of the algorithm and the three accelerations carried out achieve a speedup above 13x.

关键词： Automatic target classification and detection algorithm (ATDCA) endmember extraction hyperspectral imagery Intel oneAPI field-programmable gate arrays (FPGAs)

来源：评论

学校读者我要写书评

暂无评论

Assuring Netlist-to-Bitstream Equivalence using Physical Netlist Generation and Structural Comparison 22

Assuring Netlist-to-Bitstream Equivalence using Physical Net...

引用

22nd international conference on field programmable technology (ICFPT)

作者： McKendrick, Reilly Faulkner, Keenan Goeders, Jeffrey Brigham Young Univ Dept Elect & Comp Engn Provo UT 84602 USA

ISBN: (纸本)9798350359114

Hardware netlists are generally converted into a bitstream and loaded onto an FPGA board through vendorprovided tools. Due to the proprietary nature of these tools, it is up to the designer to trust the validity of the design's conversion to bitstream. However, motivated attackers may alter the CAD tools' integrity or manipulate the stored bitstream with the intent to disrupt the functionality of the design. This paper proposes a new method to prove functional equivalence between a synthesized netlist, and the produced FPGA bitstream. The novel approach is comprised of two phases: first, we show how we can utilize implementation information to perform a series of transformations on the netlist, which do not affect its functionality, but ensure it structurally matches what is physically implemented on the FPGA. Second, we present a structural mapping and equivalence checking algorithm that verifies this physical netlist exactly matches the bitstream. We validate this process on several benchmark designs, including checking for false positives by injecting hundreds of design modifications.

关键词： Benchmark testing Bitstream Reversal Bitstream Validation Design Verification Fasm2bels field programmable gate arrays FPGA hard-block primitives Hardware hardware trojan detection high-level circuit structures Implemented Design LEON Processor Logic gates low-level design analyses multibit signals Project X-Ray Reverse engineering Structural Comparison Trojan horses Vivado VTR benchmarks Xilinx

来源：评论

学校读者我要写书评

暂无评论

An Efficient Real-Time Pitch Correction System via field-programmable Gate Array 24

An Efficient Real-Time Pitch Correction System via Field-Pro...

引用

6th international conference on Image, Video and Signal Processing, IVSP 2024

作者： Tang, Bowen Tanaka, Kiyofumi Japan Advanced Institute Of Science And Technology Ishikawa Nomi Japan

ISBN: (纸本)9798400716829

In this paper, we present an efficient real-time pitch correction system via field-programmable Gate Arrays (FPGAs). We first analyze some of the existing methods for both pitch detection and pitch shift. We then propose novel methods, that can run in real-time with fewer hardware resources for both tasks. After examining the experiment results, we integrate both modules and implement the designed system on an FPGA board. Last, we analyze the system's hardware usage and power consumption. © 2024 ACM.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

LUTNet-RC: Look-Up Tables Networks for Reservoir Computing on an FPGA 22

LUTNet-RC: Look-Up Tables Networks for Reservoir Computing o...

引用

22nd international conference on field programmable technology (ICFPT)

ISBN: (纸本)9798350359114

We propose look-up tables networks-based reservoir computing (LUTNet-RC). This work is the first trial of applying LUTNets to RC. LUTNet-RC consists of a LUT-based reservoir layer and a non-LUT-based output layer. LUTNets have disadvantages such as limited sparse connectivity and weights cannot be changed after implementation. However, when applied to a reservoir layer of RC (LUT-based reservoir layer), these disadvantages are eliminated, because this layer works with sparse connectivity and the weights are fixed, so only the advantage of small circuit resources is obtained. For the LUT-based reservoir layer, we propose and model a multi-bit weight reservoir, modifying the conventional binarized reservoir to improve calculation accuracy. In the case of LUTNets, the proposed multi-bit weight reservoir can be implemented without the increase in utilized circuit resources because LUTNets focus only on the input-output relationship on neurons. Additionally, we propose a speed-up method in the output layer with time division calculation, which compares the current network state with previous states and then calculates only status-changed neurons. As a result, we implement a LUTNet-RC with 1500 reservoir neurons on a field-programmable gate array (KR260) running at 100MHz. The utilized circuit resources are dominated by LUTs, which use approximately 26% of the total amount of LUTs. The LUTNet-RC can infer more than 106 data per second. We also verify the LUTNet-RC performance using nonlinear auto-regressive moving average 10 (NARMA10) and the performance is comparable to conventional works. We conclude that the LUTNet-RC is one of the highest-performance RC on an FPGA.

关键词： neural networks reservoir computing field programmable gate array

来源：评论

学校读者我要写书评

暂无评论

Small-step Real-time Simulation for VSC Based on FPGA 9

Small-step Real-time Simulation for VSC Based on FPGA

引用

9th international conference on Power and Renewable Energy

作者： Hou, Yanqi Li, Kuan Fan, Deling Sun, Kongming Huang, Qiang Li, Yudun Sun, Yuntao Zhang, Guohui Shandong Smart Grid Technol Innovat Ctr State Grid Shandong Elect Power Res Inst Jinan Peoples R China

ISBN: (纸本)9798350377477;9798350377460

The voltage source converter (VSC) has been widely used in the new power system. Its electromagnetic transient simulation has the characteristics of low simulation speed and high resource consumption. In this paper, the small-step real-time simulator for VSC based on field programmable gate array (FPGA) is established. Firstly, the fixed-admittance model for VSC is established to improve the calculation speed of the primary system. At the same time, the parallel computing process of the primary system is designed to achieve small-step real-time computing of the primary system for VSC based on the parallel computing architecture of FPGA. Secondly, according to the logic of the control system for VSC, the serial-parallel computing process of the control system is designed, and the controller for VSC is implemented based on FPGA. Finally, the performance of the established FPGA simulator is verified based on the control experiments on PSCAD/EMTDC.

关键词： small-step real-time simulation voltage source converter field programmable gate array fixed-admittance model

来源：评论

学校读者我要写书评

暂无评论

A New Fixed-Point Non-Integer Downsampling Method For High-precision Harmonic analysis

A New Fixed-Point Non-Integer Downsampling Method For High-p...

引用

IEEE international Instrumentation and Measurement technology conference (I2MTC)

作者： Zou, Songting Chen, Kai Wang, Yifan Xu, Bo Zhang, Yu Qian, Lei Univ Elect Sci & Technol China Sch Automat Engn 2006 Xiyuan Ave Chengdu 611731 Peoples R China

ISBN: (纸本)9798350380903;9798350380910

Harmonic mitigation is a significant concern in industrial production and harmonic analysis plays a crucial role in power quality analysis. The achievement of accurate harmonic analysis and prevention of spectral leakage in the Fast Fourier Transform heavily relies on the utilization of synchronous sampling. This paper proposes a Fixed-point Non-integer Downsampling method, which enables dynamic downsampling while maintaining a fixed sampling rate. Based on this method, an field programmable Gate Array (FPGA) based architecture for synchronized downsampling in harmonic analysis is presented, which resolves the contradiction between the power computation requirements at high sampling rates and the synchronous data acquisition needs for harmonic analysis. The architecture is verified by experimental tests, demonstrating harmonic amplitude and phase accuracy with a relative error of 10(-7).

关键词： harmonic analysis power quality downsampling power quality analyzer field programmable Gate Array (FPGA) IEC61000-4-7

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共500页 << < 1 2 3 4 5 6 7 8 9 10 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：