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检索条件"任意字段=International Conference on Field Programmable Technology"

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FPGA Implementation of Integer Loop Delay Estimation with Low Complexity in Undersampling Digital Predistortion System 2

FPGA Implementation of Integer Loop Delay Estimation with Lo...

引用

2022 2nd international conference on Communication technology and Information technology, ICCTIT 2022

作者： Ye, Jincai Fu, Zhanming Liu, Qinghua School of Information and Communication Guilin University of Electronic Technology China

In a digital predistortion (DPD) system, accurate loop delay estimation is one of the prerequisites for precise calculation of the DPD coefficient. Multiplications of plural numbers are needed in most of the conventional loop delay estimation algorithms. Based on the Euclidean loop delay estimation (ELDE) method, this paper proposes a simplified Euclidean loop delay estimation (SELDE) method that can avoid the operation of the multiplication of plural numbers. The ELDE and SELDE method are implemented in actual undersampling systems, separately. The results of the experiments prove the feasibility and effectiveness of the methods. Compared with the ELDE method, the hardware resource consumption of SELDE is decreased, mainly reflected in the reduction of registers and look-up tables by 41.26% and 42.84%, respectively. © Published under licence by IOP Publishing Ltd.

关键词： field programmable gate arrays (FPGA)

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Visual Servoing using FPGA-based Hardware accelerated Deep Learning Solution 2

Visual Servoing using FPGA-based Hardware accelerated Deep L...

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2nd IEEE international conference on Interdisciplinary Approaches in technology and Management for Social Innovation, IATMSI 2024

作者： Saxena, Prabhav Gupta, Arjun Chadha, Shivansh Grover, Suhani Gupta, Sujal Mandpura, Anup Kumar Delhi Technological University Department of Mechanical Engineering Delhi India Delhi Technological University Department of Electronics and Communication Engineering Delhi India Delhi Technological University Department of Engineering Physics Delhi India Delhi Technological University Department of Electrical Engineering Delhi India

ISBN: (纸本)9798350360523

A novel deep-learning time-series architecture is proposed for visual servoing to control an unmanned aerial vehicle (UAV). This UAV is capable of quasi-stationary flight and is equipped with a mounted camera to track a target composed of a finite set of stationary points located in a plane. The proposed solution utilizes a time-series deep learning architecture to learn temporal data from sequential values. It then generates control cues to be sent to the flight controller, enabling the UAV to perform its tracking task. We also present an optimized implementation of the novel proposed architecture on FPGA. When it comes to implementing Neural Networks, FPGAs have demonstrated their efficiency. Specifically, our implementation is quicker than top-tier central processing units (CPUs) when it comes to carrying out the inference of the suggested model. Moreover, the proposed system also achieved improvements in terms of energy efficiency, which is important for UAV's longer endurance. © 2024 IEEE.

关键词： field programmable gate arrays (FPGA)

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Real-time Simulation and Research of Motor Controller based on FPGA 3

Real-time Simulation and Research of Motor Controller based ...

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3rd international conference on Mechanical Design and Simulation, MDS 2023

作者： Chen, Ping Chen, Yang Shi, TianCheng Civil aviation College Shenyang Aerospace University Shenyang110136 China

ISBN: (纸本)9781510664890

A hardware-in-the-loop simulation test bench based on FPGA is proposed to efficiently solve the automotive power electronics testing technology. The test bench is composed of a master control system, a real-time simulation platform, an RCP rapid prototype controller, a tested controller and an OPAL-RT solver. The simulation step can reach 1us. Automated test software can be used to set test conditions and effectively verify the performance of MCU drive and fault protection strategies, demonstrating its effectiveness. © 2023 SPIE.

关键词： field programmable gate arrays (FPGA)

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Design and Implementation of Active Phased Array Beam Steering System Based on FPGA 8

Design and Implementation of Active Phased Array Beam Steeri...

引用

8th international conference on Integrated Circuits and Microsystems, ICICM 2023

作者： Xiang, Fuxin Yao, Xiaojiang Zheng, Zilong Fan, Shenghui Zhou, Tubin Nanjing University of Posts and Telecommunications College of Integrated Circuit Science and Engineering Nanjing China Zhenjiang Research Institute Nanjing University of Posts and Telecommunications Zhenjiang China

ISBN: (纸本)9798350318517

With its precise and adaptable scanning technique, phased array radar has been extensively used in both military and civilian applications since its introduction. Phased array radar technology is simultaneously evolving toward technology, shrinking, and integration. The beam control unit, which is unquestionably a major component, surely has the same development trend. The development of the wave control code algorithm and hardware circuit design for a centralized wave control system based on the FPGA Cordic algorithm are presented in this work. Currently, the FPGA control board is used for the hardware board-level verification test, and error analysis is done by comparing the hardware verification results with Matlab computation results. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

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Comparative Study of DNN accelerators on FPGA 2

Comparative Study of DNN accelerators on FPGA

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2nd international conference on Electronic Information Engineering and Computer Communication, EIECC 2022

作者： Zhao, Yixuan Liu, Feiyang Yan, Tanbao Gao, Han Aeronautics Computing Technology Research Institute Xi'an China

ISBN: (纸本)9781510663121

As an important technology and research direction to achieve AI, deep learning has been widely applied in the fields of computer vision, speech recognition, and natural language processing. How to effectively accelerate the computing power of deep learning has always been the focus of scientific research. Among various acceleration technologies, FPGA has the advantages of reconfiguration, high performance, small size, and low latency. As more and more FPGA-based neural network accelerators are developed, we notice there is a lack of a complete and detailed overview. In this paper, we give a comparative study of DNN accelerators on FPGA from the aspects of hardware structures, design ideas and optimization strategies. We further compare the performance of different acceleration technologies in different models and present the prospects of the FPGA accelerators for deep learning. © 2023 SPIE.

关键词： field programmable gate arrays (FPGA)

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FPGA-implemented Memristor-based Transient Chaotic Neural Network for AES Edge Encryption

FPGA-implemented Memristor-based Transient Chaotic Neural Ne...

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2023 international conference on Electronics, Computers and Communication technology, CECCT 2023

作者： Wang, Hongzhe Liu, Kunsong Liu, Yi'an Wang, Junjie Sun, Mingyuan Tang, Kai Ren, Guohui Zhao, Xindi Liu, Yang State Key Laboratory of Electronic Thin Films and Integrated Devices University of Electronic Science and Technology of China Sichuan Chengdu China Beijing China Changfeng Electromechanical Technology Research and Design Beijing China China National Logging Corporation Xi an China Southwest Branch China National Logging Corporation Chongqing China

ISBN: (纸本)9798400707629

In response to the escalating demand for edge encryption in the big data era, we introduce the implementation of the Memristor-based Transient Chaotic Neural Network (MTCNN) on FPGA. This innovative approach aims to elevate the security of key generation for the Advanced Encryption Standard (AES) algorithm. Through meticulous mapping and optimization of MTCNN-AES encryption algorithm on FPGA, we achieve efficient edge encryption. Notably, the FPGA-implemented MTCNN-AES features a key space 22 orders of magnitude larger than traditional AES, underscoring its substantial resilience against brute-force attacks. The proposed approach aligns with federal information processing standards, emphasizing its reliability, robustness and randomness. © 2023 ACM.

关键词： field programmable gate arrays (FPGA)

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Customizable and programmable Deep Learning 27th

Customizable and Programmable Deep Learning

引用

27th international conference on Pattern Recognition, ICPR 2024

作者： Pal, Ratnabali Kar, Samarjit Sekh, Arif Ahmed National Institute of Technology Durgapur WB Durgapur India Brainware University WB Kolkata India Department of Graphical Systems Vilnius Gediminas Technical University Vilnius Lithuania XIM University Odisha Bhubaneswar India UiT The Arctic University of Norway Tromssa Norway

ISBN: (纸本)9783031781063

In this study, we explore the potential of pre-trained deep learning models, proposing a new approach that emphasizes their reusability and adaptability. Our framework, termed "customizable" deep learning, facilities users to seamlessly integrate diverse pre-trained models for addressing new tasks and enhancing existing solutions. Furthermore, we introduce a "programmable" adapter that enables the flexible combination of different pre-trained modules, expanding the range of applications and customization options. Through empirical experiments, particularly focusing on Visual Question Answering (VQA) for visually impaired (VI) individuals, we demonstrate the practical effectiveness of our methodology. These contributions advance the deep learning field while promoting customization and re-usability across various domains and tasks. The code is available https://***/Ratnabali-Pal/CPDA-VQA. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： Federated learning

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FPGA-Based Ultrasonic Transducer Signal IIR Filtering Treatment 3

FPGA-Based Ultrasonic Transducer Signal IIR Filtering Treatm...

引用

3rd international conference on Computer Science, Electronic Information Engineering and Intelligent Control technology, CEI 2023

作者： Liu, Ningzhuang Hu, Yuekun College of Electrical and Control Engineering Xi'an University of Science and Technology Xi'an China

ISBN: (纸本)9798350372052

During the operation of the ultrasonic transducer, factors such as temperature, load, and wear cause the resonant frequency of the transducer to deviate. Therefore, it is necessary to quickly and real-time track the resonant frequency of the ultrasonic transducer. The voltage and current signals under the working state of the transducer are severely interfered by harmonics, which greatly affects the realization of frequency tracking. Based on the principle of IIR filtering, the signal is filtered with FPGA as the core, and a digital parameter configurable IIR filter is designed for different resonant frequency transducers. The received original signal is filtered for frequency tracking. This article uses a 40kHz resonant frequency transducer as the experimental object. It has been verified that this digital filter can effectively filter out harmonic signals and has practical guiding significance for achieving frequency tracking of ultrasonic transducers. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

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A Formal Design of Parallel CRC Circuit 5

A Formal Design of Parallel CRC Circuit

引用

5th international conference on Electronic Engineering and Informatics, EEI 2023

作者： Nie, Yuchen Cai, Fangfei Zhang, Keran Zhong, Sheng Luo, Hangzai Xi'an Microelectronics Technology Institute Department of Software Engineering Xi'an710065 China Northwest University Department of Software Engineering Xi'an710127 China

ISBN: (纸本)9798350327076

Cyclic Redundancy Codes (CRCs) are useful to detect burst errors in storage and communications systems. This paper analyzes the theoretical principle of CRC and the parallel CRC structure. Besides, this paper proposes a design method for the parallel CRC, which can generate parallel CRC circuits with different parallel bit width, different CRC generating polynomial, and different input data length. The FPGA performance (LUT consumption and max frequency) of our approach is comparable to the state-of-art parallel CRC method. This paper may be useful for parallel CRC circuit design. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

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A Testbench for Stereo-Processing Acceleration Based on PYNQ and the StereoPi 12

A Testbench for Stereo-Processing Acceleration Based on PYNQ...

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12th IEEE international conference on Intelligent Data Acquisition and Advanced Computing Systems: technology and Applications, IDAACS 2023

作者： Kalomiros, John Vourvoulakis, John Vologiannidis, Stavros International Hellenic University Dpt. of Computers Informatics and Telecommunications Serres62124 Greece

ISBN: (纸本)9798350358056

Stereo processing accelerators are often designed and implemented using field programmable logic. In this paper, a new setup for the implementation and practical testing of hardware stereo-processing solutions is presented. A PYNQ Z1 board featuring a Zynq SoC is combined with a low-cost StereoPi camera. It is shown that the system is versatile, since it can exploit the optimized OpenCV capabilities of the Raspberry Pi Compute Module for image pre-processing and the hardware acceleration capabilities of the programmable Logic embedded in the Zynq chip. A series of experiments prove the feasibility of the concept. A state-of-the-art implementation of the SGM stereo algorithm in hardware description language is used in order to prove the feasibility of the design. The system can process depth maps with the nominal refresh rate of 60 fps, using stereo image resolution 640×480 and up to 96 levels of disparity. © 2023 IEEE.

关键词： FPGAs hardware design PYNQ Stereo processing StereoPi

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