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检索条件"任意字段=International Conference on Field Programmable Technology"

共 12062 条记录，以下是21-30 订阅

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A Portable Data Acquisition System for Online Wavelength Modulation Spectroscopy

A Portable Data Acquisition System for Online Wavelength Mod...

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IEEE international Instrumentation and Measurement technology conference (I2MTC)

作者： Xia, Yikai Xia, Jiangnan Xiao, Di Chen, Yuan Enemali, Godwin Liu, Chang Univ Edinburgh Sch Engn Edinburgh Midlothian Scotland Glasgow Caledonian Univ Dept Elect & Elect Engn Glasgow Lanark Scotland

ISBN: (纸本)9798350380903;9798350380910

Temperature and gas concentration are crucial parameters to be monitored in the combustion processes. As a non-intrusive laser measurement method, Wavelength Modulation Spectroscopy (WMS) has the advantages of high sensitivity, noise resistance, and fast response. To be cost-effective and flexible, it is highly demanded for an integrated, portable, and robust Data Acquisition (DAQ) system that runs without a high-level CPU. This paper aims to design a portable DAQ system using WMS for monitoring the gas parameters. The developed system consists of two main components with Ethernet communication between them: a field programmable Gate Arrays (FPGA)-based DAQ hub that digitizes, decomposes, and down-samples the measurement signal, and a Raspberry Pi that stores the data and enables online gas parameters monitoring using a data-driven neural network. The system is validated through a lab-scale combustion experiment, indicating its accuracy and efficiency.

关键词： Data Acquisition (DAQ) system Raspberry Pi field programmable Gate Arrays (FPGA) Wavelength Modulation Spectroscopy (WMS)

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Randomness Assessments for PDL-based TRNG on FPGA

Randomness Assessments for PDL-based TRNG on FPGA

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international Technical conference on Circuits/Systems, Computers, and Communications (ITC-CSCC)

作者： Yang, Heehun Park, Jiho Yoo, Hoyoung Chungnam Natl Univ Dept Elect Engn Daejeon South Korea

ISBN: (纸本)9798350379068;9798350379051

This paper investigates the enhancement of True Random Number Generators (TRNGs) in field-programmable Gate Arrays (FPGAs) through programmable Delay Logic (PDL). We examine how PDL influences the entropy quality and performance of TRNGs by controlling Ring Oscillators (ROs). Our study, conducted using Xilinx Artix-7 7A100T and Kintex Ultrascale KU040 devices, utilizes NIST SP 800-22 tests to evaluate different PDL settings. Findings demonstrate that precise PDL configurations are crucial for optimizing TRNG performance and security. This research underlines the importance of PDL in developing robust FPGA-based security systems, offering significant insights into effective digital system security enhancements.

关键词： FPGA Xilinx TRNG programmable Delay Logic

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AMARETTO: Enabling Efficient Quantum Algorithm Emulation on Low-Tier FPGAs 31

AMARETTO: Enabling Efficient Quantum Algorithm Emulation on ...

引用

31st conference on Electronics Circuits and Systems

作者： Conti, Christian Volpe, Deborah Graziano, Mariagrazia Zamboni, Maurizio Turvani, Giovanna Politecn Torino Turin Italy

ISBN: (纸本)9798350377217;9798350377200

Researchers and industries are increasingly drawn to quantum computing for its computational potential. However, validating new quantum algorithms is challenging due to the limitations of current quantum devices. Software simulators are time and memory-consuming, making hardware emulators an attractive alternative. This article introduces AMARETTO (quAntuM ARchitecture EmulaTion technology), designed for quantum computing emulation on low-tier field-programmable gate arrays (FPGAs), supporting Clifford+T and rotational gate sets. It simplifies and accelerates the verification of quantum algorithms using a Reduced-Instruction-Set-Computer (RISC)-like structure and efficient handling of sparse quantum gates. A dedicated compiler translates OpenQASM 2.0 into RISC-like instructions. AMARETTO is validated against the Qiskit simulators. Our results show successful emulation of sixteen qubits on a AMD Kria KV260 SoM. This approach rivals other works in emulated qubit capacity on a smaller, more affordable FPGA.

关键词： Quantum Computing Emulation field programmable Gate Array Quantum Algorithm Verification Quantum Computing Simulation

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Towards Automated FPGA Compilation of Spiking Neural Networks 6

Towards Automated FPGA Compilation of Spiking Neural Network...

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6th international conference on AI Circuits and Systems (AICAS)

作者： Shymyrbay, Ayan Fouda, Mohammed E. Eltawil, Ahmed King Abdullah Univ Sci & Technol CEMSE Div Dept ECE Thuwal 23955 Saudi Arabia Rain Neuromorph Inc San Francisco CA 94110 USA

ISBN: (纸本)9798350383638;9798350383645

Edge computing and the Internet of Things (IoT) have created a growing demand for low-cost and low-power field programmable gate arrays (FPGAs) to facilitate rapid and efficient processing. At the same time, spiking neural networks (SNNs) have gained popularity for their capacity to replicate biological processes and efficiently handle temporal data, making them a favorable choice in various IoT applications. However, designers must possess a comprehensive knowledge of FPGA architecture and programming methodologies to fully exploit the potential of FPGAs for SNN implementations. In this work, we propose SpiComp framework aiming to automate the implementation of SNNs on FPGAs, leveraging their reconfigurable nature and high efficiency without requiring domain expertise. Results show that the SNN implementations produced by the framework achieve high throughput and have a small energy footprint compared to other implementations in the literature while providing design automation.

关键词： spiking neural networks field programmable gate arrays design automation hardware accelerator

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Design and Realization of Multi channel programmable Power Supply SIP Based on FPGA 25

Design and Realization of Multi channel Programmable Power S...

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25th international conference on Electronic Packaging technology (ICEPT)

作者： Jiang, Shaozhuang Han, Guorong Yang, Yang Xue, Yang Jing, Qiang Shennan Circuits Co Ltd R&D Dept Shenzhen Peoples R China

ISBN: (纸本)9798350353808

Owing to its excellent parallel computing capabilities and distinctive on-site programmability, field-programmable Gate Array (FPGA) technology is deemed indispensable within specialized domains. Nonetheless, prevailing methodologies relying on discrete components to build power supply circuits for FPGA entail considerable drawbacks, including substantial footprint, elevated design expenditures, diminished stability, and pronounced electromagnetic interference, thereby circumscribing the breadth of FPGA utilization scenarios. This study endeavors to mitigate such constraints by devising a Power Management System-in-Package (SIP) featuring multiple independent and configurable power rails, tailored to the power exigencies of large-scale FPGA characterized by high core current demands and different power supply voltage levels for multiple BANKs. The proposed system integrates nine DC-DC units and one LDO unit to furnish autonomous power delivery to ten distinct power rails, each offering individually adjustable outputs. Programming control is realized through the utilization of compact logic devices for power enablement and millisecond-level timing management. The buried PCB technology is applied to encapsulate multiple active and passive devices into a single module measuring 22mmx22mmx7.4mm. Experimental evaluation of the module's VOUT1 reveals an approximate conversion efficiency of 89.2% under typical output conditions of 1V10A. When configured solely with 2x22uF ceramic capacitors and subjected to a substantial load of 20A, the observed output ripple remains <= 1.95%. The module boasts a maximum total output power of 125W and exhibits robust operational stability within an environmental range spanning from -55 degrees C to 85 degrees C, with a notable maximum shock resistance acceleration exceeding >= 5000g. The embedded power module implemented in this study features multiple power rails, robust environmental stability, and rapid deployment capabilities, thereby

关键词： power supply module programmable multiple power rails rapid deployment

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Design of A High Performance Time-to-Digital Converter with Zero Dead Time on Xilinx FPGA

Design of A High Performance Time-to-Digital Converter with ...

引用

IEEE international Instrumentation and Measurement technology conference (I2MTC)

作者： Qi, Xinren Wang, Yonggang Univ Sci & Technol China Dept Modern Phys State Key Lab Particle Detect & Elect Hefei Peoples R China

ISBN: (纸本)9798350380903;9798350380910

Nowadays the time-to-digital converters (TDCs) implemented on field programmable gate array (FPGA) can achieve reasonably high measurement resolution and precision. However, some applications also require TDCs without measurement dead time to avoid event missing. In this paper, we propose a new TDC design method that can achieve high measurement precision while achieving zero measurement dead time as well. Using the traditional structure of tapped delay line (TDL) based TDC, the proposed TDC allows consecutive trigger signals flowing into the TDL and makes the encoder capable of capturing all trigger edges with the output of their timestamps. Since there is the inherent "bubble" problem in TDL for high performance implementation, the latched TDL status is first decomposed into sixteen divisions. The trigger edges on the divisions are identified parallel, and then all the trigger signals on the TDL have to be reinstalled to obtain their precise arrival times. The TDC has been implemented on a Xilinx Zynq Ultrascale+ FPGA for performance evaluation. The test results show that the TDC can achieve a resolution of 1.92 ps and a root mean square (RMS) precision better than 3.3 ps. By measuring two trigger signals located within one TDC sampling clock cycle, the TDC can measure them correctly, which means the proposed design method is effective for realizing zero measurement dead time.

关键词： field programmable gate array time-to-digital converter zero dead time

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Advancing machine learning tasks with field-programmable gate arrays: advantages, applications, challenges, and future perspectives 2

Advancing machine learning tasks with field-programmable gat...

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2nd international conference on Electrical, Electronics, and Information Engineering, EEIE 2023

作者： Ma, Da University of Toronto 27 King's College Cir TorontoONM5S 1A1 Canada

ISBN: (纸本)9781510672840

This article comprehensively explores the applications, advantages, and challenges of using field-programmable Gate Arrays (FPGAs) to enhance machine learning tasks. It fills a gap in the existing literature by conducting a systematic review of the current FPGA utilization for the latest machine learning frameworks. The review provides valuable insights for researchers, highlighting the next steps regarding FPGA utilization in machine learning and its potential expansion to other areas. This article showcases case studies and research examples to demonstrate the effectiveness of FPGAs in different stages of machine learning, including data preprocessing, feature extraction, model training, and real-time neural network inference, and cutting-edge applications in the related field. Looking ahead, the future of FPGA research holds promise for further advancements in efficiency, performance, and the integration of FPGA technology with other hardware accelerators to meet the evolving demands of machine learning. © 2024 SPIE.

关键词： Machine learning

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Inverter-Based Switched Current programmable Sampled and Hold Amplifier for LV Applications 25

Inverter-Based Switched Current Programmable Sampled and Hol...

引用

25th IEEE international conference on Industrial technology, ICIT 2024

作者： Abdel-Fattah, Mo'men F. Farag, Fathi A. Egypt Japan University Of Science And Technology Electronics And Communications Department Egypt Zagazig University Electronics And Communications Department Egypt

ISBN: (纸本)9798350340266

In this paper, a programmable current mode Sample Hold (SH) circuit is proposed. The proposed SH is based on the Switched Inverter technique [1], [2]. The circuit employs the conventional CMOS inverter operating as I/V and V/I converter with the current mirror concept. In the proposed circuit, the switches are worked at fixed channel voltage therefore, the switch conduction gap can be overcome. Moreover, the introduced cell structure presents class-AB operation which has low power ability consumption. Delay unit with a fully programmable coefficient (positive and negative), which is employed in FIR filter for channel equalizer or sampled data integrator for analog circuit designing. The proposed circuits are implemented by using a single CMOS inverter and capacitor, therefore, achieving the ability of a field programmable Analog Array (FPAA) circuit. The circuit is designed to be fabricated in 130 nm CMOS technology. The designed circuits (SH, delay unit, and integrator) are worked under 750 mV as a supply voltage with optimum low power consumption. © 2024 IEEE.

关键词： Timing circuits

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Design and Analysis of Efficient On-Star Compression Algorithms for FPGA Platforms 2

Design and Analysis of Efficient On-Star Compression Algorit...

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2nd international conference on Computer Vision and Intelligent technology

作者： Zhang, Guoliang Wang, Xueying Fan, Jianpeng Natl Univ Def Technol Coll Elect Sci & Technol Changsha Peoples R China

ISBN: (纸本)9798331540050;9798331540043

Image compression has always been a hot topic in the field of aerospace. The onboard processing unit, due to its background of deep space operation, has greatly limited performance in terms of data storage and data transmission. Satellite remote sensing images are developing towards larger size, higher frame frequency, and more frequency bands, which increasingly demand storage space and processing power. There is an urgent need for a set of efficient and lightweight image compression hardware and software. Therefore, in this work, we have improved the Context-Based Adaptive Lossless Image Compression (CALIC) algorithm, including error quantization and entropy coding, to meet the requirements for on-orbit processing in terms of compression time and compression ratio. At the same time, aiming at the working scenario of on-orbit processing, we chose field-programmable Gate Array (FPGA) as the platform to deploy the improved CALIC and designed the arithmetic coding Av value calculation process in parallel on this basis, which greatly reduced the processing time on the hardware side. We have carried out simulation verification of this paper's image compression algorithm on the KODAK24 and SZTAKI_Airchange datasets. The experimental results show that our method strikes a good balance between compression ratio and compression rate compared with typical compression algorithms, making it suitable for on-orbit processing scenarios.

关键词： field-programmable Gate Array Image Compression Remote Sensing Image CALIC

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Integration of a Trojan Detection Tool with BFDS: Enhancing field-programmable Gate Array Security 24

Integration of a Trojan Detection Tool with BFDS: Enhancing ...

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4th international conference on Artificial Intelligence, Automation and Algorithms

作者： Zhang, Yanlong Xiao, Ke Wang, Shuo Zhou, Jing Beijing Microelect Technol Inst Beijing Peoples R China

ISBN: (纸本)9798400717840

field-programmable gate arrays (FPGAs) have garnered considerable interest and utilization, largely owing to their inherent flexibility and customizability. In this context, electronic design automation (EDA) technology serves as an instrumental facilitator for FPGA applications. Nevertheless, the emergence of hardware Trojans (HTs) represents a major vulnerability in FPGA security. To mitigate the risks associated with hardware Trojans, a formula has been devised to compute the controllability and observability of each signal within logic units in look-up table (LUT) netlists. Subsequently, a security verification methodology aimed at HT detection within these LUT netlists has been developed and incorporated into the EDA tool, BFDS. Detailed procedural steps for HT detection, including interactions with the graphical user interface, are elucidated. The efficacy of this embedded HT detection tool is substantiated through experimental validation. The results from these experiments confirm the capacity of the tool to successfully identify Trojans at the LUT-level netlist while seamlessly integrating into EDA toolchains, thereby enhancing the security of future FPGA design endeavors.

关键词： hardware Trojan detection electronic design automation tool graphical user interface

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