检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

11,988 篇 会议
70 篇 期刊文献

馆藏范围

12,058 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

5,961 篇 工学
- 4,622 篇 计算机科学与技术...
- 2,163 篇 电子科学与技术（可...
- 2,127 篇 软件工程
- 1,661 篇 电气工程
- 1,107 篇 信息与通信工程
- 841 篇 控制科学与工程
- 447 篇 机械工程
- 442 篇 仪器科学与技术
- 207 篇 动力工程及工程热...
- 183 篇 材料科学与工程（可...
- 177 篇 光学工程
- 163 篇 生物医学工程（可授...
- 154 篇 生物工程
- 113 篇 航空宇航科学与技...
- 101 篇 建筑学
- 80 篇 土木工程
- 74 篇 安全科学与工程
- 69 篇 化学工程与技术
1,557 篇 理学
- 785 篇 数学
- 521 篇 物理学
- 182 篇 系统科学
- 158 篇 生物学
- 111 篇 统计学（可授理学、...
- 78 篇 化学
564 篇 管理学
- 512 篇 管理科学与工程(可...
- 125 篇 工商管理
- 64 篇 图书情报与档案管...
205 篇 医学
- 142 篇 临床医学
- 79 篇 基础医学(可授医学...
77 篇 经济学
- 76 篇 应用经济学
63 篇 法学
48 篇 文学
31 篇 农学
29 篇 教育学
20 篇 军事学
7 篇 艺术学

主题

7,266 篇 field programmab...
3,464 篇 field programmab...
2,297 篇 hardware
1,041 篇 clocks
1,006 篇 computer archite...
512 篇 signal processin...
496 篇 table lookup
420 篇 throughput
419 篇 random access me...
408 篇 algorithm design...
349 篇 logic gates
349 篇 ofdm
345 篇 registers
339 篇 routing
325 篇 hardware design ...
317 篇 modulation
296 篇 estimation
284 篇 switches
268 篇 real-time system...
260 篇 digital signal p...

机构

42 篇 school of inform...
40 篇 department of co...
35 篇 chitkara univers...
30 篇 university of ch...
25 篇 department of el...
24 篇 school of comput...
23 篇 harbin institute...
21 篇 school of engine...
21 篇 beijing institut...
20 篇 institute of vls...
18 篇 graduate school ...
17 篇 fudan univ state...
17 篇 institute of mic...
16 篇 beijing key labo...
16 篇 school of electr...
15 篇 university of sc...
15 篇 school of inform...
14 篇 department of co...
14 篇 school of automa...
13 篇 department of el...

作者

61 篇 wayne luk
37 篇 luk wayne
25 篇 motoki amagasaki
25 篇 masahiro iida
19 篇 minoru watanabe
18 篇 liji wu
18 篇 yu wang
18 篇 gurdeep singh
17 篇 n. masmoudi
16 篇 chao wang
16 篇 amanpreet kaur
15 篇 yang jun
15 篇 suhaib a. fahmy
15 篇 wang lingli
14 篇 iouliia skliarov...
14 篇 george a. consta...
14 篇 valery sklyarov
14 篇 saniie jafar
13 篇 wang lei
13 篇 paul chow

语言

11,859 篇 英文
124 篇 中文
74 篇 其他
1 篇 俄文

检索条件"任意字段=International Conference on Field Programmable Technology"

共 12058 条记录，以下是291-300 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

FPGA-Based High-Speed Infrared Image Acquisition and Transmission Design 2

FPGA-Based High-Speed Infrared Image Acquisition and Transmi...

引用

2nd international conference on Artificial Intelligence and Computer Information technology, AICIT 2023

作者： Ye, Gang Zhang, Tianxu Fang, Lu School of Electrical and Information Enginerring WuHan Institute of Technology WuHan China School of Artificial Intelligence and Automation Huazhong University of Science and Technology WuHan China

ISBN: (纸本)9798350302950

With the rapid development of electronic technology and computer vision technology, the requirements for real-time and fast image acquisition are increasing, and it is difficult to implement on a dedicated integrated chip with long development cycle, while the design features of FPGA parallel pipeline, in addition to low power consumption and low cost of the chip, make the real-time and fast image acquisition and transmission on FPGA chips are guaranteed. The interface between the infrared detector and the FPGA acquisition system uses the industrial high-speed serial data and connection protocol Camera Link interface, and due to the very large amount of data transmission, an easy-to-use Gigabit Ethernet port is used as the interface between the high-speed transmission system and the host computer. The system is implemented under VIVADO2019 software, and the logic functions are developed using hardware description language, in addition to the modelsim simulation verification. In the normal operation of the system: the system can achieve high speed image acquisition and transmission, and the image acquisition reaches 50 frames per second, and the transmission to the host computer can also display the image processing results in real time, which has high practical application value. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Concurrent Architecture of High Speed Viterbi Decoder Using Xilinx HLS Tool 4

Concurrent Architecture of High Speed Viterbi Decoder Using ...

引用

4th IEEE international conference on Artificial Intelligence in Engineering and technology, IICAIET 2022

作者： Zunzunwala, Jyoti Joshi, Atul S. Sipna College of Engineering and Technology Department of Electronics and Telecommunication Engg. Amravati India

ISBN: (数字)9781665468374

ISBN: (纸本)9781665468374

Viterbi decoder finds its applications in different areas like radio communication, satellite communication, hard disk drives and automatic speech recognitions. The general building blocks implementing the Viterbi decoder are the Branch Metric Unit, Path Metric Unit and Traceback Unit. Viterbi decoder becomes possible because it uses maximum likelihood decoding to interpret the coded message, but, on the other hand, is considered to be the high resource consuming block. To address this issue, in the proposed research work, concurrent architecture of the Viterbi decoder is proposed. The architecture is described using hardware description language and it is targeted to the Kintex series field programmable Gate Arrays (FPGA) which are fabricated at 28nm technology. For describing the architecture Xilinx Vivado High Level Synthesis (HLS) tool is preferred. The outcome of the proposed architecture is evaluated using different ascendency parameters like time, frequency, power utilization and resource utilization. © 2022 IEEE.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

FPGA Based Multi-Functional and Multi-Dimensional Smart Network Routing Processor 8

FPGA Based Multi-Functional and Multi-Dimensional Smart Netw...

引用

8th IEEE international conference on Computational System and Information technology for Sustainable Solutions, CSITSS 2024

作者： Achar, Sumana Jayadevappa, D. Jss Academy of Technical Education Dept. of Electronics & Inst. Engg. Bengaluru India Dr. Nh National College of Engineering Bengaluru India

ISBN: (纸本)9798331505462

Data traffic is recurring and increasing issue of the network when multiple users wants to use the limited bandwidth of the communication system. Handling the data is important so that the there can be efficient delivery of data by routers. Routers now are either hybrid Routers or software routers which are mostly dependent of operating system of the server. Many research has been done, claimed and evaluated to optimize software routing algorithms that are used to find the nearest or best forwarding path for the data to be routed in a topology of the network. Usually, Data plane operates at high speed and are implemented on Hardawre and control plane that processes router functionalities are at slower pace, implemented using softwares and need a processor to execute them. We propose a model of router architecture where both data plane and control plane operates on hadware and is CPU-independeat. This proposed router is multi-functional, multi-dimensional, multi-protocol support. System. This plug and play network router is an intelligent to analyse the data and route accordingly. The proposed router is implemented on FPGA so that the router can be made scalable and reprogrammable for design re-use. We claim that the router performance will improve comparaed to software- algorithm based routers. © 2024 IEEE.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Compressor based Approximate Multipliers for Neural Network Accelerators

Compressor based Approximate Multipliers for Neural Network ...

引用

2024 international conference on Advancements in Power, Communication and Intelligent Systems, APCI 2024

作者： Chintagunta, Munikantha Kota, Venkata Ramanaiah Vemu Institute of Technology Department of Ece P.Kothakota Andhra Pradesh Chittoor India Yogi Vemana University Department of Ece Ysr Engineering College YSR District Andhra Pradesh Proddatur India

ISBN: (纸本)9798350363289

As several image and video processing applications gain popularity, the approximate computing has gained importance to effectively utilize the available channel bandwidth. As multipliers are the computationally intensive components of neural networks, the aim of this paper remains to approximate it and reduce the number of components utilized for its implementation. This paper proposes six approximate multipliers based on approximation of 4 to 2 compressors for Neural Networks. The design 1 utilizes exact 8x8 multiplier with 2, 3 and 4-input AND, XOR and OR gates for approximate compressor with 6.25% error, The design 2 utilizes only 2-input XOR, AND and OR gates for approximate compressor with 37.5% error. The designs 3 to 6 are the combinations of multiplexer based approximations carried out with an error of '5.8% to 20%. The designs are developed in Verilog HDL and implemented for 28nm high-K CMOS technology based Zynq FPGA (XC7Z100-2FFG1156) in Xilinx Vivado Tool. The proposed design 5 proves to be reliable along with the less total path delay of at least by 2.47% to 7.81% and the power dissipation being minimum by at least 5.6% to 14.02%. How ever design 5 trades off area by 2.98% to 6.94%, where design 6 proves to be a good choice. From results, the proposed designs 5 and 6 to be good choice for approximate multipliers. © 2024 IEEE.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

A Framework for Enabling Artificial Intelligence Inference for the Hardware Acceleration of IVIS Imaging System 1

引用

5th international conference on Advances in Distributed Computing and Machine Learning, ICADCML 2024

作者： Mathew, Rani Rachel Sharmila Banu, K. Tripathy, B.K. Thomas, Lijo Lajitha, C.S. Daniel, Jerry Amity Private School Sharjah United Arab Emirates Vellore Institute of Technology Vellore India CIG CDAC Trivandrum India

ISBN: (数字)9789819718412

ISBN: (纸本)9789819718405

Machine Vision Cameras are an essential component in the chain of industrial image processing to optimize and automatically monitor manufacturing processes. The Industrial Vision Sensor (IVIS) was developed by C-DAC, Thiruvananthapuram, which must be equipped with the proper artificial intelligence-based approaches in order to serve the next-generation industrial vision applications. In this paper, we present an ideal framework for existing IVIS imaging systems to produce artificial intelligence-based inferences that will meet requirements like throughput, latency, power, and better processing capability. © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2024.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

XNPU - EXtensible Neural Processing Unity from a programmable Logic Device

XNPU - EXtensible Neural Processing Unity from a Programmabl...

引用

2022 IEEE international conference on Consumer Electronics, ICCE 2022

作者： Cruz, Thiago S. Gomes, Joao P. M. Suassuna, Hugo G. M. Albuquerque, Danyllo W. Dos Santos Junior, Gutemberg G. Perkusich, Angelo Santos, Danilo F. S. Federal University of Campina VIRTUS RDI Center Grande Brazil

ISBN: (纸本)9781665441544

As an emerging field of machine learning, deep learning represents a powerful technique to solve complex learning problems. However, the size of the networks becomes increasingly large due to the demands of the practical applications, which poses a significant challenge to construct high-performance implementations of deep learning neural networks. In order to improve the performance as well as to maintain the low power cost, in this paper we design a neural processing unit, which is a scalable accelerator architecture for large-scale deep learning networks using the field-programmable Gate Array (FPGA) as the hardware prototype. © 2022 IEEE.

关键词： Deep learning

来源：评论

学校读者我要写书评

暂无评论

Research and Implementation of FPGA-based Local Adaptive Thresholding

Research and Implementation of FPGA-based Local Adaptive Thr...

引用

2023 international conference on Machine Vision, Image Processing and Imaging technology, MVIPIT 2023

作者： Zhu, Wangchun Hu, Chang Guilin University of Electronic Science and Technology Guilin School of Electronic Engineering and Automation China

ISBN: (纸本)9798350306545

In view of the problems of the current fixed threshold algorithm, which is prone to clustering effect caused by uneven distribution of ambient light, unable to distinguish the foreground and background of the image, and unable to extract a large number of feature points, this paper adopts the innovative design of accelerating algorithm processing of verilog HDL hardware circuit platform. The innovation of the algorithm lies in using the average value of local extreme points and the texture feature of the whole image to adapt to the changes of complex environment in real time. The experimental results show that after the image is processed by the local adaptive image algorithm, the feature point information of the target contour can still be well extracted when the image is interfered by the uneven distribution of light. The similarity fitting of the feature point of the contour can reach 86%, which is improved compared with the fixed threshold of 73%. There are no obvious breakpoints, voids, white noise and other problems, and a relatively complete image is displayed. At the same time, the image target can be easily recognized when the background and foreground colors are switched. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

AES Algorithm for the Next Generation of 5G Network Encryption Standards 2

AES Algorithm for the Next Generation of 5G Network Encrypti...

引用

2nd IEEE international conference on Advances in Computing, Communication and Applied Informatics, ACCAI 2023

作者： Manojkumar, T. Tamilarasi, K. Mahalakshmi, S. Vinayagam, P. Mahanthesha, U. Mohanraj, S. Karpagam Institute of Technology Department of Electronics and Communication Engineering Tamilnadu Coimbatore India Excel Engineering College Department of Electronics and Communication Engineering Tamilnadu Namakkal India R.M.K. Engineering College Department of Computer Science and Design Tamilnadu Chennai India Saveetha Engineering College Department of Electronics and Communication Engineering Tamilnadu Chennai India Bnm Institute of Technology Department of Artificial Intelligence and Machine Learning Karnataka Bengaluru India Rajalakshmi Engineering College Department of Electronics and Communication Engineering Tamilnadu Chennai India

ISBN: (纸本)9798350315905

The Advanced Encryption Standard (AES) symmetric key encryption algorithm is the industry standard for 5G communication encryption. technology advancements nowadays are mostly aimed at improving the security, speed, and efficiency of processors. The main expansion phase is made easier by the study's pipeline structure. This method simplifies the process of creating subkeys in AES encryption for use in 5G communication networks. There is a 37% increase in throughput between the simulated and implemented versions of the original design on FPGA Virtex4 XC4VLX200, and this difference may be attributed to the reduction in propagation latency while producing subkeys. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Design of Real-time Centroid Extraction System for Shack-Hartmann Sensor Based on FPGA 3

Design of Real-time Centroid Extraction System for Shack-Har...

引用

3rd IEEE international conference on Electronic technology, Communication and Information, ICETCI 2023

作者： Xiaocui, Shen Zhangqin, Huang Han, Gao Beijing University of Technology Beijing Engineering Research Center for IoT Software and Systems Beijing China

ISBN: (纸本)9798350398410

Hartmann wavefront sensor is applied widely in adaptive optics systems. Considering the real-time performance requirements and processing amount of Hartmann sensors in computing the centroids of points, this article proposes an FPGA-based real-time image processing and centroid extraction system. The system adopts FPGA as the core processor and uses the connected domain labeling algorithm and the gray centroid method to complete the centroid calculation. In addition, the calculation results are output simultaneously through multiple DAs to drive the device under test to achieve image wavefront restoration. At the same time, the image data is uploaded to the host computer in real-time through the Ethernet interface. The system has excellent performance in real-time image processing, image output quality, and system control stability. Experiments show that it is an efficient technical means of providing real-time wavefront processing measurement for the Hartmann sensor in various application scenarios, such as adaptive optical correction. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

An error verification design of DDC based on MATLAB and FPGA 3

An error verification design of DDC based on MATLAB and FPGA

引用

3rd international conference on Advanced Algorithms and Signal Image Processing, AASIP 2023

作者： Deng, Rendi Tang, Rui School of Mechanical and Electrical Engineering Chengdu University of Technology Chengdu610059 China School of Electronic Information Engineering China West Normal University Nanchong637002 China

ISBN: (纸本)9781510668522

The main work of this paper is to study the error verification problem of radar echo signal DDC algorithm implementation, and DDC has certain innovations in hardware implementation methods. The main design modules of DDC include band-pass filtering, mixing, low-pass filtering, decimation and zeroing. In the design and verification of DDC system, the time-domain dual-frequency chirp echo signal is first simulated, and the DDC processing process is verified by advanced floating-point simulation on the MATLAB platform to verify its feasibility and correctness. Then, through Verilog HDL programming, the FPGA-based DDC implementation is carried out, and the output results of each module are simulated through Medelsim. Finally, the simulation results in each FPGA module are calculated with the simulation results in MATLAB to verify the accuracy of the hardware design. © COPYRIGHT SPIE. Downloading of the abstract is permitted for personal use only.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共500页 << < 26 27 28 29 30 31 32 33 34 35 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：