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international conference on field programmable technology

作者： Xu, Chang Zhang, Wentai Luo, Guojie Peking Univ Sch EECS Ctr Energy Efficient Comp & Applicat CECA Beijing 100871 Peoples R China PKU UCLA Joint Res Inst Sci & Engn Beijing Peoples R China

ISBN: (纸本)9781479962457

In this paper we propose a quantitative approach to analyze the impact of heterogeneous blocks (H-blocks) on the FPGA placement quality. The basic idea is to construct synthetic heterogeneous placement benchmarks with known optimal wire-length to facilitate the quantitative analysis. To the best of our knowledge, this is the first work that enables the construction of wirelength-optimal heterogeneous placement examples. Besides analyzing the quality of existing placers, we further decompose the impacts of H-blocks from the architectural aspect and netlist aspect. Our analysis shows that a heterogeneous design hides the wirelength degradation by a more compact netlist than its homogeneous version;however, the heterogeneity results in a optimality gap of 52% in wirelength, where 25% is from architectural heterogeneity and 27% is from netlist heterogeneity. Therefore, new heterogeneous placement algorithms are needed to bridge the optimality gap and improve design quality.

关键词： field programmable gate arrays (FPGA)

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AUSTRALIAN SKA PATHFINDER: DIGITAL SIGNAL PROCESSING IMPLEMENTATION AND EARLY ENGINEERING TEST ARRAY RESULTS

AUSTRALIAN SKA PATHFINDER: DIGITAL SIGNAL PROCESSING IMPLEME...

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IEEE international conference on Acoustics, Speech and Signal Processing (ICASSP)

作者： Tuthill, J. Bateman, T. Brown, A. Bunton, J. D. Hampson, G. Hotan, A. Neuhold, S. Reynolds, J. Shimwell, T. Voronkov, M. CSIRO Astron & Space Sci Melbourne Vic Australia

ISBN: (纸本)9781479928934

The Boolardy Engineering Test Array (BETA) is the first prototype of the Australian Square Kilometer Array Pathfinder (ASKAP), a new radio telescope that is pioneering the use of Phased Array Feed (PAF) technology in radio astronomy to provide instantaneous wide field-of-view imaging. BETA consists of six 12 meter parabolic antennas, each equipped with a 188-element PAF at the focus and a signal processing system capable of imaging an instantaneous 7 square degree field-of-view with a bandwidth of 300MHz at a resolution of 18kHz. In this paper we describe the architecture of the digital signal processing chain and its implementation on reconfigurable hardware based on field-programmable Gate Array (FPGA) technology. We present early engineering results taken by the instrument during commissioning trials at the Murchison Radio Observatory (MRO) in remote Western Australia. In particular, we present the first multi-beam image of an astronomical source captured with a PAF-based interferometer.

关键词： Phased arrays field programmable gate arrays Channel bank filters Array signal processing Radio astronomy

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FPGA Interconnect Modeling for Lifetime Failure Detection

FPGA Interconnect Modeling for Lifetime Failure Detection

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IEEE international conference on Electro/Information technology (EIT)

作者： Vittala, Kavya Vemuru, Srinivasa Niamat, Mohammed Univ Toledo Dept Elect Engn & Comp Sci 2801 W Bancroft St Toledo OH 43606 USA Ohio Northern Univ Dept Elect & Comp Engn & Comp Sci Ada OH 45810 USA

ISBN: (纸本)9781479947744

As FPGAs move into nanometer regime CMOS technology, new performance and lifetime limitations have started showing up. The process variation effects cause undesired behavior of the circuit as transistor dimensions decrease. This work makes an effort to understand the importance of routing in FPGAs and its impact on the performance of nanometer scale FPGAs. Lifetime failure of FPGAs can be detected by observing the variation in the delay performance from newly developed or developing faults. In this paper, we develop models of interconnect and switching networks that enhance delay estimation. Circuit simulations performed using these models are compared with the timing simulation results from Xilinx development tools.

关键词： Delays field programmable gate arrays Integrated circuit interconnections Integrated circuit modeling Routing Table lookup Wires field programmable gate arrays Table lookup integrated circuit interconnections integrated circuit modelling Network routing Rope ELECTRIC WIRE delay Defect detection process change

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Multiple contexts in a multi-ported VLIW register file implementation

Multiple contexts in a multi-ported VLIW register file imple...

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international conference on Reconfigurable Computing and FPGAs (ReConFig)

作者： Joost Hoozemans Jens Johansen Jeroen Van Straten Anthony Brandon Stephan Wong Technische Universiteit Delft Delft Zuid-Holland NL Computer Engineering Lab Delft University of Technology The Netherlands Computer Engineering Lab Delft University of Technology Delft Zuid-Holland NL

The register file is an expensive component in the design of any processor, especially, when considering the additional ports that are needed to support multiple datapaths within a wide-issue VLIW processor. In a recent work, these additional resources were used to dynamically reconfigure the register file to support a dynamically reconfigurable VLIW core. The design can be perceived as a single 8-issue, two 4-issue, or four 2-issue VLIW cores. Consequently, the multi-ported design can operate in different modes, namely as one, two, or four register files, respectively, corresponding to the active number of cores. The implementation of the register file design on FPGAs using Block RAMs still results in unused resources due to the coarseness of the Block RAMs. In this paper, we propose to re-purpose these unused BRAM resources to additionally support multiple contexts next to earliermentioned modes. In this manner, the 8-issue, 4-issue, and 2- issue cores have access to 4, 2, and 1 contexts, respectively. Consequently, we can avoid saving and restoring of the task states in a multi-task environment, turning context switching from a traditionally time-consuming event to an almost instantaneous event. The advantage of this is the reduction of interrupt latency and task switching latency, which are important in real-time and embedded systems. Our results show that our technique can improve interrupt latency by a factor of 17.4x compared to using a software register spill routine, depending on the behavior of the memory system. Likewise, the task switching time can be improved by 6.7x.

关键词： Registers Context Switches VLIW field programmable gate arrays Random access memory Real-time systems

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FPGA methodology for power analysis of embedded adaptive beamforming

FPGA methodology for power analysis of embedded adaptive bea...

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international conference on Communications, Signal Processing, and their Applications (ICCSPA)

作者： Owais Talaat Waheed Ayman Shabra Ibrahim M. Elfadel Institute Center for Microsystems (iMicro) Masdar Institute of Science & Technology Abu Dhabi UAE Khalifa University of Science and Technology - Masdar City Campus Masdar City Abu Dhabi AE

In wireless communication systems, multipath and interference effects degrade the SNR and increase the BER of received signals. Antenna arrays and beamforming algorithms are typically used to improve system performance and noise immunity. For non-adaptive beamforming where signal-path gains remain unchanged, power dissipation is predictable but SNR and BER depend on the changing statistics of the received signals. On the other hand, in adaptive beamforming where signal-path gains are changed in real time according to the statistics of the received signals, the SNR is improved and BER is decreased, but power dissipation undergoes unpredictable transients during the gain adaptation process. Such transients are especially detrimental to battery-based power management systems in mobile applications. In this paper, we propose an FPGA-based methodology for the analysis, modeling and prediction of power dissipation in embedded array signal processing systems containing adaptive beamforming components. This FPGA-based methodology enables the exploration of the adaptive beamforming design space in terms of power, timing, overhead, arithmetic precision and computational resources. A distinct feature of this methodology is that it enables such design-space exploration in real-time and on actual received waveforms. We describe a specific implementation of this methodology using a hardware prototype based on Xilinx's Virtex 7 FPGA. We use this prototype to explore the design space of a four-channel Least-Mean-Squares (LMS) beamformer. The main result of this exploration is the selection of an adaptive algorithm design point that represents the best tradeoff between parameter convergence, machine precision and energy-efficiency for the embedded array signal processor.

关键词： Array signal processing Least squares approximations Convergence Algorithm design and analysis field programmable gate arrays Power dissipation Software packages

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Stub-series terminated logic based energy Efficient Devnagri Unicode Reader design on 40nm and 28nm FPGA

Stub-series terminated logic based energy Efficient Devnagri...

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international conference on Next Generation Computing Technologies (NGCT)

作者： Nisha Sharma Bhanisha Verma Amanpreet Kaur Department of ECE Haryana Engineering College Jagadhri India Department of ECE Chitkara University Rajpura India

It has been observed that amongst all the 22 languages being used Devanagari script is being the primary and most widely used script. Devanagari is used for writing the Hindi language in India. In this paper Energy Efficient Devanagari Unicode Reader has been designed. Devanagari is used for writing the Hindi language in India. In this paper Devanagari Unicode Reader code has been implemented on Xilinx ISE Design Suite 14.2 and the results of 28nm FPGA platform has been compared with the 40nm technology. Impedances of transmission line, port and device should be equal in order to avoid reflection in transmission line which is a usual problem in hardware design. So SSTL logic family has been used at input and output ports so as to avoid such reflections. The power analyses had been done at different frequencies ranging from 1 THZ to 1 MHZ using different IO standards of SSTL logic family. Out of 40nm (Virtex -6) and 28nm(Artix-7),maximum power has been saved in case of 28nm(Artix-7) when the device is operating at frequency of 1MHZ on SSTL18 I IOstandard.

关键词： Standards field programmable gate arrays Power demand Frequency measurement Next generation networking Computers Clocks

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Development of a New High Speed Dual-Channel Impulse Ground Penetrating Radar

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IEEE JOURNAL OF SELECTED TOPICS IN APPLIED EARTH OBSERVATIONS AND REMOTE SENSING 2014年第3期7卷 753-760页

作者： Venkatachalam, Anbu Selvam Xu, Xianlei Huston, Dryver Xia, Tian Univ Vermont Sch Engn Burlington VT 05405 USA

This paper presents the development of a dual channel, air coupled Ultra-Wideband (UWB) Ground Penetrating Radar (GPR) targeting highway pavements and bridge deck inspections. Compared to most existing GPRs with a single channel and low survey speeds, our GPR possesses competitive features, including wide area coverage, high spatial resolution and operating capability at normal highway driving speed (up to 60 mph). The system has a two-channel microwave front end, a high speed (8 Gsps) real time data acquisition unit, a high throughput multi-thread data transmission and storage module, and a customized low-cost control element developed in a field-programmable gate array (FPGA). Experiments with different steel reinforcing bars establish GPR system performance.

关键词： field-programmable gate array ground penetrating radar ultra-wideband (UWB)

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FPGA-based SHA-3 acceleration on a 32-bit processor via instruction set extension

FPGA-based SHA-3 acceleration on a 32-bit processor via inst...

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IEEE conference on Electron Devices and Solid-State Circuits

作者： Yi Wang Youhua Shi Chao Wang Yajun Ha Agency for Science Technology and Research Singapore SG Waseda Daigaku Shinjuku-ku Tokyo JP

As embedded systems play more and more important roles Internet of Things (IoT), the integration of cryptographic functionalities is an urgent demand to ensure data and information security. Recently, Keccak was declared as the winner of the third generation of Secure Hashing Algorithm (SHA-3). However, implementing SHA-3 on a specific 32-bit processor failed to meet the performance requirement. On the other hand, implementing it as a cryptographic coprocessor consumes a lot of extra area and requires customized driver program. Although implementing Keccak on a 64-bit platform is more efficient, this platform is not suitable for embedded implementation. In this paper, we propose a novel SHA-3 implementation using instruction set extension based on a 32-bit LEON3 processor (an open source processor), with the goals of reducing execution cycles and code size. Experimental results show that the proposed design reduces around 87% execution cycles and 10.5% code size as compared to reference designs. Our design takes up only 9.44% extra area with negligible speed overhead compared to the standard LEON3 processor. Compared to the existing hardware accelerators, our proposed design occupies only half of area resources and does not require extra driver programs to be developed when integrated into the overall system.

关键词： Hardware Registers Algorithm design and analysis Cryptography field programmable gate arrays Throughput Acceleration

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Efficient multi-standard cognitive radios on FPGAs 24

Efficient multi-standard cognitive radios on FPGAs

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24th international conference on field programmable Logic and Applications, FPL 2014

作者： Pham, Thinh H. Fahmy, Suhaib A. McLoughlin, Ian Vince School of Computer Engineering Nanyang Technological University Singapore Singapore School of Information Science and Technology University of Science and Technology of China Hefei China

ISBN: (纸本)9783000446450

Cognitive radios that support multiple standards and modify operation depending on environmental conditions are becoming more important as the demand for higher bandwidth and efficient spectrum use increases. Traditional implementations in custom ASICs cannot support such flexibility, with standards changing at a faster pace, while software baseband implementations fail to achieve the performance required. Hence, FPGAs offer an ideal platform bringing together flexibility, performance, and efficiency. This work explores the possible techniques for designing multi-standard radios on FPGAs, and explores how partial reconfiguration can be leveraged in a way that is amenable for domain experts with minimal FPGA knowledge. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Reconfigurable data processing using duplex fault tolerance system

Reconfigurable data processing using duplex fault tolerance ...

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international conference on Innovations in Information,Embedded and Communication Systems (ICIIECS)

作者： M. Shobana Murugan.S Senthil Valliammai Engineering college Anna University India Valliammai Engineering college Anna University Chennai India

Many digital signal processor designers and manufacturers are facing one big challenge, that is, how to perform complex mathematical function calculations more efficiently. To gain efficiency, it is needed to dig inside our complete designing cycle which contains algorithms, architectures, hardware technology, power supply etc. Fast Fourier Transform (FFT) is widely used transform in digital applications especially in communication systems. An FFT is an important processing block in these systems, which takes most of the hardware complexity in a digital baseband transceiver for instance. Half duplex is one of the redundancy based architecture. The duplex fault tolerance system is used to detect and localization of faulty module which leads to reconfigure the faulty module. Our adapted duplex system is used as a basic structure to increase availability parameters and protect system against single even upsets (SEUs). In the paper, the SEU simulation framework for testing fault tolerant system designs implemented into FPGA is presented. The SEU simulator does not require any changes in the tested design and is fully independent on the function implemented into FPGA SEU generator and its properties are described in the paper as well. The external SEU generator for Xilinx FPGA was implemented and verified on evaluation board ML506 with Virtex5 for different types of RTL circuits and fault tolerant architectures. The experimental results demonstrated the effectiveness of the methodology.

关键词： field programmable gate arrays Algorithm design and analysis Discrete Fourier transforms Multiplexing Computer architecture

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