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检索条件"任意字段=International Conference on Field Programmable Technology"

共 12062 条记录，以下是41-50 订阅

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Design and FPGA implementation of digital AGC in sonar receivers 4

Design and FPGA implementation of digital AGC in sonar recei...

引用

4th international conference on Sensors and Information technology, ICSI 2024

作者： Ma, Kuixu Du, Jinyan Liu, Zeqi Li, Shengxin He, Chuanlin Institute of Oceanographic Instrumentation Qilu University of Technology Shandong Academy of Sciences Qingdao266061 China Weihai264209 China Qingdao Op-Sens Ocean Science & Technology Co Ltd. Qingdao266318 China

ISBN: (数字)9781510678699

ISBN: (纸本)9781510678682

In addressing the issue of gradually attenuating amplitude of underwater acoustic signals received by hydrophones, this paper presents a feedforward digital automatic gain control (AGC) system based on a table lookup method. This approach reduces significant computational load associated with logarithmic operations, multiplication, and floating-point arithmetic. The system was simulated using MATLAB software, and the results indicate that, compared to the commonly used binary search-based digital AGC systems, the feedforward digital AGC system based on the table lookup method exhibits faster control speed, smoother output signals, and a noticeable reduction in signal transients. Finally, a comparative validation of the two algorithms was conducted on field programmable Gate Array (FPGA), confirming the applicability and outstanding performance of the feedforward digital AGC system based on the table lookup method in practical engineering applications. © 2024 SPIE.

关键词： field programmable gate arrays (FPGA)

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A Novel Delay-Aware Packing Algorithm for FPGA Architecture Using RFET 67

A Novel Delay-Aware Packing Algorithm for FPGA Architecture ...

引用

67th IEEE international Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Lu, Sheng Shang, Liuting Jung, Sungyong Zhang, Yichen Pan, Chenyun Univ Texas Arlington Dept Elect Engn Arlington TX 76019 USA

ISBN: (纸本)9798350387186;9798350387179

Reconfigurable devices are gaining increasing attention as a viable alternative and supplementary solution to traditional CMOS technology. In this paper, we develop a more efficient 2-input look-up table (LUT) based on the reconfigurable field-effect transistors (RFETs), leading to a smaller transistor usage and a smaller critical path delay. The cells are organized into regular matrices, known as MClusters, with a fixed interconnection pattern to replace LUTs in field-programmable gate arrays (FPGAs). To improve the efficiency of utilizing this structure, we design a SAT-based delay-aware packing algorithm to better utilize logical gates for the MCluster structure. Finally, we combine this algorithm with FPGA simulation tools to form a comprehensive benchmarking flow. A series of benchmark tests show that under the optimal design, up to 35% and 30% reduction can be achieved in delay and energy-delay product (EDP), respectively, compared to the traditional CMOS FPGAs.

关键词： Reconfigurable FET field-programmable gate arrays look-up table partitioning algorithm packing algorithm technology mapping performance benchmarking

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CYNQ: Speeding Up FPGA Applications With Simplicity 31

CYNQ: Speeding Up FPGA Applications With Simplicity

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31st conference on Electronics Circuits and Systems

作者： Leon-Vega, Luis G. Avila-Torres, Diego Leon-Vega, Indra Castro-Godinez, Jorge Univ Trieste Math Informat & Geosci Dept Trieste Italy Univ Estatal Distancia Informat Sch Liberia Costa Rica Inst Tecnol Costa Rica Sch Ind Design Engn Cartago Costa Rica Inst Tecnol Costa Rica Sch Elect Engn Cartago Costa Rica

ISBN: (纸本)9798350377217;9798350377200

FPGAs for hardware acceleration face several issues in their adoption by the emerging AI embedded software community, mainly due to the difficulty of getting started in the field. To address these issues, FPGA vendors have tried to simplify and combine workflows to make them user-friendly. This has also impacted the runtime libraries used on Linux to allow user space applications to interact with FPGA programmable logic. However, this approach can result in suboptimal results, given the added overhead in single-purpose applications in an attempt to generalise the runtime libraries. This work presents CYNQ Runtime Library, a simplistic and API-agnostic C/C++ runtime library with the ease of PYNQ and the efficiency of C++ and XRT. In comparison to most popular runtime libraries for AMD FPGAs, our work outperforms PYNQ and XRT with more than 5.34x speedup in execution latency and more than 1.20x in large workloads than XRT, which poses a better scenario for high-performance single-purpose applications.

关键词： field programmable Gate Arrays Hardware Acceleration Edge Computing Cloud Computing High Performance Computing

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A Configurable CPG Controller using Connectome based SNN on FPGA for Robot Locomotion 9

A Configurable CPG Controller using Connectome based SNN on ...

引用

9th Annual IEEE international conference on Rebooting Computing, ICRC 2024

作者： Ereifej, Joseph Araujo, Kevin Nadji-Tehrani, Mohammad Kubendran, Rajkumar University of Pittsburgh PittsburghPA United States Neuraville Inc PittsburghPA United States

ISBN: (纸本)9798331541279

Movement control in autonomous robots requires low-power, real-time models, especially for bio-mimetic locomotion in challenging terrains. Human intervention is often impractical in such environments, making specialized neural networks like central pattern geterators critical for offloading computational resources. This paper presents a controller for a bipedal robot using a modified spiking neuron model, adapted for efficient deployment on field-programmable gate arrays. Key modifications were made to ensure lightweight, real-time performance. Additionally, we leverage a unique open-source neuromorphic software platform for the network design and deployment, making the technology accessible to developers aiming to implement autonomous robot locomotion. © 2024 IEEE.

关键词： field programmable gate arrays (FPGA)

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Implementation and Applications of Neural Networks Based on FPGA

Implementation and Applications of Neural Networks Based on ...

引用

2024 international conference on Electrical Drives, Power Electronics and Engineering, EDPEE 2024

作者： Li, Jiajun Zhang, Chuhuan Ma, Xiangcheng Shenzhen College Of International Education Shenzhen China Nanjing University Of Aeronautics And Astronautics Nanjing China

ISBN: (纸本)9798350395631

Deep neural networks have been crucial in several recent developments in artificial intelligence and big data technology, including natural language processing, speech recognition, and computer vision. Given the numerous layers of deep neural network models, the computational complexity, and a large number of parameters, the performance of hardware such as computing power, memory bandwidth, and data storage is highly demanding. Due to their high parallelism, low power consumption, and reconfigurability, field programmable Gate Arrays (FPGAs), which are programmable logic devices, are frequently used as an alternative to CPUs and GPUs. Their combination with neural networks has become a current research hotspot in the field of artificial intelligence. This paper briefly describes firstly the current mainstream neural network models and the design ideas of FPGAs. Next, the applications of FPGA-based neural networks are introduced. Finally, this paper concludes with a summary and outlook on the development of FPGA-based applications for deep neural networks. © 2024 IEEE.

关键词： Deep neural networks

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INDUSTRIAL ROBOT CONTROL SYSTEM RESEARCH BASED ON THE DIRECTION OF programmable LOGIC CONTROLLERS

INDUSTRIAL ROBOT CONTROL SYSTEM RESEARCH BASED ON THE DIRECT...

引用

2024 international conference on Electrical Engineering and Intelligent Control, EEIC 2024

作者： Hu, Letian School of Electronics and Information Xijiao Liverpool University Anhui Hefei230000 China

ISBN: (纸本)9781837242672

With the rise of the intelligent manufacturing industry, industrial robots have also become a new development trend in today's industrial production and manufacturing technology. To understand and enhance the level of automation of industrial robots in the production process, to further achieve the precise control and coordination of the industrial production process. This paper combines industrial robots and automated operation and control under the guidance of programmable Logic Controllers (PLC) technology, as an example, to explore some of the applications and characteristics of PLC technology in industrial robots, and on this basis, in-depth excavation of the current status of the application of the technology and the prospects for development. In addition, this paper also found some of the current PLC control technology and industrial robotics applications in the field of problems, such as PLC control technology has low compatibility and the operator interface is not convenient enough, industrial robots in the existing industrial production and manufacturing technology is not enough precision, and in the production process may receive electromagnetic or noise interference and other issues. At the same time, some examples illustrate the use of PLC-related technology to solve the above problems, such as the use of soft PLC technology to improve the compatibility of the control system the convenience of the operator interface, and so on. This paper can provide new research ideas and innovative points for the two technologies in the future development and promote the further development of PLC technology in industrial robotics. © The Institution of Engineering & technology 2024.

关键词： programmable logic controllers

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Introduction to the Special Issue on the 11th international conference on field-programmable technology (FPT'12)

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ACM TRANSACTIONS ON RECONFIGURABLE technology AND SYSTEMS 2014年第3期7卷 18-18页

作者： Anderson, Jason Choi, Kiyoung Univ Toronto Toronto ON M5S 1A1 Canada Seoul Natl Univ Seoul 151 South Korea

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Research on Testing technology of Embedded Processor Cache Controller in programmable SoC 3

Research on Testing Technology of Embedded Processor Cache C...

引用

3rd IEEE international conference on Information technology, Big Data and Artificial Intelligence, ICIBA 2023

作者： Song, Xingzuo Li, Xuewu Chen, Lei Sun, Huabo Zhang, Fan Beijing Microelectronics Technology Institute Beijing China

ISBN: (纸本)9781665490788

With the progress of Integrated Circuit technology and the multiple needs of human for scalar and reconfigurable operations in intelligent electronic system, a new chip architecture combining traditional FPGA and embedded processor appears, namely programmable SoC. programmable SoC products have been widely used in mission and safety-critical applications, but production defects in hardware and time-related defects in the working process often lead to system misbehavior, which leads to disastrous consequences. Therefore, in view of the long-term reliability application requirements of programmable SoC products, it is necessary to carry out relevant research on its in-field test technology. In this paper, we will use the Software-Based Self Test (SBST) method to explore and implement the function of data cache controller for Zynq-7000 series programmable SoC embedded processors (Enable\Disable, Invalidate, Clean) test technology research. By making full use of the fully programmable features of hardware and software resources in Zynq-7000, we have respectively realized the test generation technology based on PS and the test observation technology based on PL, and designed the prototype test system. Finally, the experimental results show that the prototype test system meets our expectations and can realize the in-field test of the cache controller of the embedded processor in the Zynq-7000 series programmable SoC. At the end of this paper, we summarize the work done and look forward to the future research direction. © 2023 IEEE.

关键词： System-on-chip

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Fully parallel implementation of digital memcomputing on FPGA 67

Fully parallel implementation of digital memcomputing on FPG...

引用

67th IEEE international Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Nguyen, Dyk Chung Pershin, Yuriy, V Univ South Carolina Dept Phys & Astron Columbia SC 29208 USA

ISBN: (纸本)9798350387186;9798350387179

We present a fully parallel digital memcomputing solver implemented on a field-programmable gate array (FPGA) board. For this purpose, we have designed an FPGA code that solves the ordinary differential equations associated with digital memcomputing in parallel. A feature of the code is the use of only integer-type variables and integer constants to enhance optimization. Consequently, each integration step in our solver is executed in 96 ns. This method was utilized for difficult instances of the Boolean satisfiability (SAT) problem close to a phase transition, involving up to about 150 variables. Our results demonstrate that the parallel implementation reduces the scaling exponent by about 1 compared to a sequential C++ code on a standard computer. Additionally, compared to C++ code, we observed a time-to-solution advantage of about three orders of magnitude. Given the limitations of FPGA resources, the current implementation of digital memcomputing will be especially useful for solving compact but challenging problems.

关键词： field programmable gate arrays nonlinear dynamical systems computing technology

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A Zero Trust Architecture employing Blockchain and Ring Oscillator Physical Unclonable Function for Internet-of-Things

A Zero Trust Architecture employing Blockchain and Ring Osci...

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IEEE international conference on Electro Information technology (EIT)

作者： Kulkarni, Akshay Niraula, Amrit Bhattarai, Hrishav Niamat, Mohammed Univ Toledo Dept EECS 2801 W Bancroft St Toledo OH 43606 USA

ISBN: (纸本)9798350330656;9798350330649

The Internet-of-Things (IoT) constitute a network of millions of devices interconnected through the internet to facilitate data transfer amongst themselves. This network, along with the devices involved in it, is vulnerable to various cyber threats, due to its high utilization. Consequently, notable research is being conducted to enhance the security of IoT devices and networks. The state-of-the-art, however, still lacks a reliable solution against insider threats in the IoT network. This paper introduces a zero-trust architecture implemented by blockchain and ring oscillator physical unclonable functions (ROPUFs) to bolster the security of IoT devices and networks. The zero trust policies are inspired by the tenets outlined by the National Institute of Standards and technology. The unique challenge response pairs generated by ROPUFs are utilized to validate the FPGAs. Blockchain features, such as smart contracts, tracking and tracing capabilities, and immutability, are employed for user authentication and access control. To assess the successful implementation of the proposed technique, a case study of an image file transfer between two users is presented. This scenario is effectively simulated using the Ganache framework provided by the Truffle suite. For implementing the ROPUF, Artix 7 Xilinx FPGA mounted on Nexys 4 Digilent board is used. The blockchain smart contract for this investigation is developed using the Solidity language.

关键词： blockchain field programmable gate array internet-of-things ring oscillator physical unclonable functions zero trust architecture

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