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Development of a New High Speed Dual-Channel Impulse Ground Penetrating Radar

IEEE JOURNAL OF SELECTED TOPICS IN APPLIED EARTH OBSERVATIONS AND REMOTE SENSING 2014年第3期7卷 753-760页

作者： Venkatachalam, Anbu Selvam Xu, Xianlei Huston, Dryver Xia, Tian Univ Vermont Sch Engn Burlington VT 05405 USA

This paper presents the development of a dual channel, air coupled Ultra-Wideband (UWB) Ground Penetrating Radar (GPR) targeting highway pavements and bridge deck inspections. Compared to most existing GPRs with a single channel and low survey speeds, our GPR possesses competitive features, including wide area coverage, high spatial resolution and operating capability at normal highway driving speed (up to 60 mph). The system has a two-channel microwave front end, a high speed (8 Gsps) real time data acquisition unit, a high throughput multi-thread data transmission and storage module, and a customized low-cost control element developed in a field-programmable gate array (FPGA). Experiments with different steel reinforcing bars establish GPR system performance.

关键词： field-programmable gate array ground penetrating radar ultra-wideband (UWB)

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FPGA-based SHA-3 acceleration on a 32-bit processor via instruction set extension

FPGA-based SHA-3 acceleration on a 32-bit processor via inst...

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IEEE conference on Electron Devices and Solid-State Circuits

作者： Yi Wang Youhua Shi Chao Wang Yajun Ha Agency for Science Technology and Research Singapore SG Waseda Daigaku Shinjuku-ku Tokyo JP

As embedded systems play more and more important roles Internet of Things (IoT), the integration of cryptographic functionalities is an urgent demand to ensure data and information security. Recently, Keccak was declared as the winner of the third generation of Secure Hashing Algorithm (SHA-3). However, implementing SHA-3 on a specific 32-bit processor failed to meet the performance requirement. On the other hand, implementing it as a cryptographic coprocessor consumes a lot of extra area and requires customized driver program. Although implementing Keccak on a 64-bit platform is more efficient, this platform is not suitable for embedded implementation. In this paper, we propose a novel SHA-3 implementation using instruction set extension based on a 32-bit LEON3 processor (an open source processor), with the goals of reducing execution cycles and code size. Experimental results show that the proposed design reduces around 87% execution cycles and 10.5% code size as compared to reference designs. Our design takes up only 9.44% extra area with negligible speed overhead compared to the standard LEON3 processor. Compared to the existing hardware accelerators, our proposed design occupies only half of area resources and does not require extra driver programs to be developed when integrated into the overall system.

关键词： Hardware Registers Algorithm design and analysis Cryptography field programmable gate arrays Throughput Acceleration

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Efficient multi-standard cognitive radios on FPGAs 24

Efficient multi-standard cognitive radios on FPGAs

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24th international conference on field programmable Logic and Applications, FPL 2014

作者： Pham, Thinh H. Fahmy, Suhaib A. McLoughlin, Ian Vince School of Computer Engineering Nanyang Technological University Singapore Singapore School of Information Science and Technology University of Science and Technology of China Hefei China

ISBN: (纸本)9783000446450

Cognitive radios that support multiple standards and modify operation depending on environmental conditions are becoming more important as the demand for higher bandwidth and efficient spectrum use increases. Traditional implementations in custom ASICs cannot support such flexibility, with standards changing at a faster pace, while software baseband implementations fail to achieve the performance required. Hence, FPGAs offer an ideal platform bringing together flexibility, performance, and efficiency. This work explores the possible techniques for designing multi-standard radios on FPGAs, and explores how partial reconfiguration can be leveraged in a way that is amenable for domain experts with minimal FPGA knowledge. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Reconfigurable data processing using duplex fault tolerance system

Reconfigurable data processing using duplex fault tolerance ...

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international conference on Innovations in Information,Embedded and Communication Systems (ICIIECS)

作者： M. Shobana Murugan.S Senthil Valliammai Engineering college Anna University India Valliammai Engineering college Anna University Chennai India

Many digital signal processor designers and manufacturers are facing one big challenge, that is, how to perform complex mathematical function calculations more efficiently. To gain efficiency, it is needed to dig inside our complete designing cycle which contains algorithms, architectures, hardware technology, power supply etc. Fast Fourier Transform (FFT) is widely used transform in digital applications especially in communication systems. An FFT is an important processing block in these systems, which takes most of the hardware complexity in a digital baseband transceiver for instance. Half duplex is one of the redundancy based architecture. The duplex fault tolerance system is used to detect and localization of faulty module which leads to reconfigure the faulty module. Our adapted duplex system is used as a basic structure to increase availability parameters and protect system against single even upsets (SEUs). In the paper, the SEU simulation framework for testing fault tolerant system designs implemented into FPGA is presented. The SEU simulator does not require any changes in the tested design and is fully independent on the function implemented into FPGA SEU generator and its properties are described in the paper as well. The external SEU generator for Xilinx FPGA was implemented and verified on evaluation board ML506 with Virtex5 for different types of RTL circuits and fault tolerant architectures. The experimental results demonstrated the effectiveness of the methodology.

关键词： field programmable gate arrays Algorithm design and analysis Discrete Fourier transforms Multiplexing Computer architecture

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High speed, flexible, robust and low power processing approach

High speed, flexible, robust and low power processing approa...

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international Microsystems, Packaging, Assembly and Circuits technology (IMPACT)

作者： Knaji Otsuka Yoichi Sato Meisei University Collaborative Research Center Hino-shi Tokyo Japan

We are all longing for high speed, flexible, robust and low power processing system in the world. FPGA architecture is gathering attention due to one order less magnitude of power saving as one of non-Neumann approach. Other approach is like unified block included small logic, small memory and small controller which is announced by eASIC, nextrame-2/3(1) or Synopsis, EVP(2) as examples which are instead of many core Neumann architecture. These trends originate due to extremely lower power operation and elimination of band width wall between logic and memory. Our study is also for the same unified block that makes only memory with look up table (LUT) and small controller configuration(3). Using no logic circuit means LUT instead that is named “Memory-Logic Conjugated System (MLCS)”. The key of the concept is to make minimal function cluster of LUT array by SRAM circuit base that is significant to keep the highest efficiency. This can be seen one time to logic and other time to memory depending on the dynamical change of need. Dynamic reconfiguration can be led in only several clocks, that produces flexible system. Huge or tinny configurations are designed fairly easy to proper block arrangement by each application. These are also coming true redundant systems followed robust. As constructed memory, running power is very low as two orders less of magnitude than Neumann processor. High speed processing can be done by elimination of the band width wall because neighboring block job area is easy to communicate with each other. This will be presented with some of detail.

关键词： field programmable gate arrays Table lookup Random access memory Robustness Clocks Power demand Redundancy

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Hardware conversion of neural networks simulation models for neural processing accelerator implemented as FPGA-based SoC 24

Hardware conversion of neural networks simulation models for...

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24th international conference on field programmable Logic and Applications, FPL 2014

作者： Pietras, Marcin Computer Science and Information Technology West Pomeranian University of Technology ZUT Szczecin Poland

ISBN: (纸本)9783000446450

The transition from a neural network simulation model to its hardware representation is a complex process, which touches computations precision, performance and effective architecture implementation issues. Presented neural processing accelerator involves neural network sectioning, precision reduction and weight coefficients parsing (arrangements) in order to increase efficiency and maximize FPGA hardware resources utilization. Particular attention has been devoted on to ANN conversion methods designed for a system based on neural processing units and related with this process redundant calculations and empty neurons generation. In addition, this paper describes the FPGA-based Neural Processing Accelerator architecture benchmark for real example implementation of a pattern recognition neural network. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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FlipSyrup: Cycle-accurate hardware simulation framework on abstract FPGA platforms 24

FlipSyrup: Cycle-accurate hardware simulation framework on a...

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24th international conference on field programmable Logic and Applications, FPL 2014

作者： Takamaeda-Yamazaki, Shinya Kise, Kenji Nara Institute of Science and Technology Japan Tokyo Institute of Technology Japan

ISBN: (纸本)9783000446450

FPGA-based rapid prototyping is widely applied for fast simulations of hardware structure verifications. In this paper, we propose flipSyrup, a prototyping framework for cycle-accurate hardware simulations on abstract FPGA platforms. In order to mitigate the development complexity of FPGA-based simulators, the framework provides two abstractions of resources on FPGA platforms: Memory systems and inter-FPGA interconnections on multi-FPGA platforms. The framework enables designers to draw up a target hardware using abstract interfaces as ideal memory systems and interconnections on FPGA platforms. Our evaluation result shows that the slowdowns in simulation speed under the abstractions by using the framework are not critical. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring 13

Memory Security in Reconfigurable Computers: Combining Forma...

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international conference on field programmable technology

作者： Wiersema, Tobias Drzevitzky, Stephanie Platzner, Marco Univ Paderborn Paderborn Germany

ISBN: (纸本)9781479962457

Ensuring memory access security is a challenge for reconfigurable systems with multiple cores. Previous work introduced access monitors attached to the memory subsystem to ensure that the cores adhere to pre-defined protocols when accessing memory. In this paper, we combine access monitors with a formal runtime verification technique known as proof-carrying hardware to guarantee memory security. We extend previous work on proof-carrying hardware by covering sequential circuits and demonstrate our approach with a prototype leveraging ReconOS/Zynq with an embedded ZUMA virtual FPGA overlay. Experiments show the feasibility of the approach and the capabilities of the prototype, which constitutes the first realization of proof-carrying hardware on real FPGAs. The area overheads for the virtual FPGA are measured as 2x-10x, depending on the resource type. The delay overhead is substantial with almost 100x, but this is an extremely pessimistic estimate that will be lowered once accurate timing analysis for FPGA overlays become available. Finally, reconfiguration time for the virtual FPGA is about one order of magnitude lower than for the native Zynq fabric.

关键词： Formal verification field programmable gate arrays Memory Memory time series analysis Computer hardware configurability core Overlay Virtual

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An Efficient FPGA Implementation of QR Decomposition using a Novel Systolic Array Architecture based on Enhanced Vectoring CORDIC 13

An Efficient FPGA Implementation of QR Decomposition using a...

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international conference on field programmable technology

作者： Zhang, Jianfeng Chow, Paul Liu, Hengzhu Natl Univ Def Techonol Coll Comp Changsha Hunan Peoples R China Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9781479962457

Multiple input multiple output (MIMO) - Orthogonal frequency division multiplexing (OFDM) systems typically use Orthogonal-triangular (QR) decomposition. In this paper, we present a novel systolic array architecture to realize QR decomposition based on the Givens rotation method for a 4 x 4 real matrix. The coordinate rotation digital computer (CORDIC) algorithm is adopted and modified to speed up and simplify the Givens rotation. To verify the function and evaluate the performance, the proposed architectures are validated on a Virtex 5 FPGA development platform. Compared to a commercial implementation of vectoring CORDIC, an enhanced vectoring CORDIC is presented that uses 37.7% less hardware resources, dissipates 76.8% less power and provides a 1.8 times speed-up while maintaining the same computation accuracy. The novel QR systolic array architecture based on the enhanced vectoring CORDIC saves 5% in hardware and the throughput is improved by a factor of two with no accuracy penalty when compared with the best previous version of the QR systolic array.

关键词： field programmable gate arrays (FPGA)

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Low-latency option pricing using systolic binomial trees 13

Low-latency option pricing using systolic binomial trees

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international conference on field programmable technology

作者： Tavakkoli, Aryan Thomas, David B. Imperial Coll London Dept Elect & Elect Engn Circuits & Syst Res Grp London England

ISBN: (纸本)9781479962457

This paper presents a novel reconfigurable hardware accelerator for the pricing of American options using the binomial-tree model. The proposed architecture exploits both pipeline and coarse-grain parallelism in a highly efficient and scalable systolic solution, designed to exploit the large numbers of DSP blocks in modern architectures. The architecture can be tuned at compile-time to match user requirements, from dedicating the entire FPGA to low latency calculation of a single option, to high throughput concurrent evaluation of multiple options. On a Xilinx Virtex-7 xc7vx980t FPGA this allows a single option with 768 time steps to be priced with a latency of less than 22 micro-seconds and a pricing rate of more than 100 K options/sec. Compared to the fastest previous reconfigurable implementation of concurrent option evaluation, we achieve an improvement of 65 X in latency and 9 X in throughput with a value of 10.7 G nodes/sec, on a Virtex-4 xc4vsx55 FPGA.

关键词： Pricing Latency field programmable gate arrays User needs Throughput Systole Digital signal processing Desmoplakin Gene pipeline Binomial modern architectures Large Numbers hardware accelerator

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