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检索条件"任意字段=International Conference on Field Programmable Technology"

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A Heterogeneous Integration System of Analog in-Memory Computing and field-programmable Gate Array 17

A Heterogeneous Integration System of Analog in-Memory Compu...

引用

17th IEEE international conference on Solid-State and Integrated Circuit technology, ICSICT 2024

作者： Chen, Hua Qu, Yiming Wu, Wenhao Zhao, Yi School of Integrated Circuits East China Normal University Shanghai200241 China China Nanhu Academy of Electronics and Information Technology Jiaxing314001 China College of Information Science and Electronic Engineering Zhejiang University Hangzhou310027 China

ISBN: (纸本)9798350361834

With the development of deep learning models, deploying neural networks to resource-limited edge devices has become a trend. However, the high computation requirements and energy consumption of neural network models have limited their development. Analog In-Memory Computing (AIMC) features high energy efficiency, providing new opportunities for the edge deployment of neural networks. The system needs to support different types of neural network models in practical applications, and the system-level application is still immature. This paper proposes a heterogeneous system integrating analog in-memory computing and field-programmable Gate Array (FPGA). The system reserves multiple sensor interfaces for access and preprocessing peripherals, including digital NN accelerators and AIMC, which can effectively execute various layers in neural network models, achieving complete end-to-end neural network inference. Depending on the size and number of FC layers, the system has varying degrees of improvement in inference time and RAM occupation. © 2024 IEEE.

关键词： Multilayer neural networks

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Managing Cloud Networks: A Classification of SDN-Enabled Clouds 5

Managing Cloud Networks: A Classification of SDN-Enabled Clo...

引用

5th IEEE international conference on Computing, Power, and Communication Technologies, IC2PCT 2024

作者： Singh, Vaishali Kehkeshan Jallal, S. Das, Sunanda Maharishi University of Information Technology Maharishi School of Engineering & Technology Uttar Pradesh India Presidency University Department of Electronics and Communication Engineering Karnataka Bangalore India Faculty of Engineering and Technology Department of Computer Science Engineering Karnataka Bangalore India

ISBN: (纸本)9798350383522

The idea of separating the management plane from the data-forwarding gear was first introduced by Software-Defined Networking (SDN), which has brought about a revolutionary new age in networking. This innovation makes networks programmable, flexible, and dynamically reconfigurable. These characteristics have great potential for the field of computer science in the cloud, where dynamic adjustments and reconfiguration are essential owing to on-demand consumption patterns. The many simulation and empirical assessment techniques that have been created expressly for SDN-enabled cloud settings are also highlighted by us. Finally, study conducted perform a critical review of the state of the research, highlighting gaps and suggesting possibilities for further study. © 2024 IEEE.

关键词： application framework cloud computing hardware resources programmable controller resource provisioning simulation and energy modeling Software-Defined Networking (SDN)

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ATP-Optimized Four-Term Karatsuba Multipliers for Large Integer Arithmetic on FPGAs 1

ATP-Optimized Four-Term Karatsuba Multipliers for Large Inte...

引用

1st international conference on Electronics, Communication and Signal Processing, ICECSP 2024

作者： Patel, Saubi Singh, Shubham Kumar, Sumit Das, Monalisa Jajodia, Babita Indian Institute of Information Technology Guwahati Department of Electronics and Communication Engineering Bongora Guwahati India

ISBN: (纸本)9798350364590

This work presents two methods of hardware implementation of area-time-product (ATP)-optimized four-term Karatsuba multipliers (FTKM) on field programmable Gate Arrays (FPGAs). This is done by eliminating the effects of complexity of sub-multiplications present at the intermediate steps of computation. Besides these, hardware implementation of the proposed work suggests that the proposed FTKM multiplication methods (FTKM-I and FTKM-II) performs better in terms of resource utilization and delay minimization compared to other existing state-of-the-art multiplication methods, irrespective of input bit lengths. Hardware implementations of the proposed FTKM methods (FTKM-I and FTKM-II) multiplication architecture are demonstrated on a Virtex-7 FPGA device in Xilinx ISE platform. Here, the hardware implementation of the proposed FTKM multipliers is carried out for 128 bits, 256 bits, 512 bits, and 1024 bits, showcasing advantages in area-time-product (ATP) over previous research. ATP serves as the Figure-of-Merit (FoM) for determining the performance of the design. © 2024 IEEE.

关键词： field programmable gate arrays (FPGA)

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FPGA-based decision-making for efficient satellite orientation and propulsion 2

FPGA-based decision-making for efficient satellite orientati...

引用

2nd IEEE international conference on Vision Towards Emerging Trends in Communication and Networking Technologies, ViTECoN 2023

作者： Okade, Samanyu Adithya Narayan, M. Ragunath, G. School of Electronics Engineering Vellore Institute of Technology Vellore India

ISBN: (纸本)9798350347982

field programmable Gate Arrays (FPGAs) are board-based hardware implementations of Very Large-Scale Integration (VLSI) that have greatly flexible computing capabilities. To show its ability to perform multifarious functions together, this paper proposes the design for a prototype that uses light input from multiple onboard light sensors around the device or satellite. This information is used in terms of the intensity of light detected by the sensors and their associated angles of reading to activate the actuators involved in the orientation of the solar panels and cold gas thrusters to get the most efficient positioning for sunlight to be the best incident on the solar panels. This is an alternative name to the use of FPGA in space technology other than for the currently prevalent data processing. The goal of this paper is to promote the multifunctional use of FPGAs in the vast field of space technology and its scope for the furtherment of human exploration of outer space. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

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Deep unfolding based microwave imaging with spin-decoupled programmable metasurface 7

Deep unfolding based microwave imaging with spin-decoupled p...

引用

7th IEEE international conference on Electronic Information and Communication technology, ICEICT 2024

作者： Zhang, Fan Feng, Weike Wang, Chaohui Liu, Tong Pu, Tao Gao, Huanhuan Wang, Zhengjie Xu, He-Xiu Air Force Engineering University Xi'an China

ISBN: (纸本)9798350384437

In this paper, the deep unfolding (DU) based microwave imaging method for near-field objects using 1-bit spin-decoupled programmable metasurface (SPM) is studied. First, a 1-bit SPM operating at 12 GHz is designed. Then, the theoretical imaging model is established using the plane-wave angular spectrum approach. Finally, the imaging methods based on the iterative shrinkage-thresholding algorithm (ISTA) and the learned ISTA are presented. By comparing the imaging results obtained by different methods, it is verified that the designed SPM equipped with the DU method is a promising technique for microwave imaging with excellent performance. © 2024 IEEE.

关键词： Microwave irradiation

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Design and Simulation of RISC Processor Using Verilog 5

Design and Simulation of RISC Processor Using Verilog

引用

5th international conference on Inventive Research in Computing Applications, ICIRCA 2023

作者： Sudhanya, P. Kumar, Aryan Sharma, Tushar Agrawal, Akshat Srm Institute of Science and Technology Faculty of Engineering and Technology Department of Electronics and Communication Engineering Kattankulathur603203 India

ISBN: (纸本)9798350321425

Reduced Instruction Set Computer (RISC) Processors have recently become quite an important aspect of keeping up with all the advances in technology. This research presents a comprehensive study on the design and simulation of an improved RISC processor architecture on field-programmable Gate Arrays (FPGAs). The objective is to enhance the performance, efficiency, and versatility of RISC processors by incorporating novel design techniques and optimizations. The proposed design mainly focuses on the improved design of the Arithmetic and Logic Unit (ALU). The effectiveness of the proposed design is evaluated through extensive simulations. The results demonstrate significant improvements in performance in time and total power. The findings of this study indicate that the improved RISC processor design offers a promising approach to address the increasing demands of modern computing systems. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

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FPGA Implementation of High-Bandwidth Fast Current Control Without Computational Delay 7

FPGA Implementation of High-Bandwidth Fast Current Control W...

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7th IEEE international Electrical and Energy conference, CIEEC 2024

作者： Gong, Xubo Wang, Wei Huang, Yonghe Xu, Dianguo Harbin Institute of Technology Electrical Engineering Harbin China

ISBN: (纸本)9798350359558

In the field of PMSM control, the current loop bandwidth represents the dynamic performance of the servo system. In this paper, based on the mathematical model, it is proved that the effective way to widen the current loop bandwidth under the condition of constant switching frequency is to reduce the computational delay of the current loop. In this paper, an improved piecewise and instant PWM duty cycle update method based on FPGA is proposed to reduce the complexity of the current loop computation when multi-sampling and multi-update are performed, which can effectively reduce the Computational delay, and the method can also improve the system DC bus voltage utilization. The feasibility of this method has been verified by experiments under different current conditions in permanent magnet synchronous motor. © 2024 IEEE.

关键词： field programmable gate arrays (FPGA)

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VVRMA: VR field Trip to a Computer Music Center

VVRMA: VR Field Trip to a Computer Music Center

引用

international conference on New Interfaces for Musical Expression, NIME 2024

作者： Kim, Kunwoo Wang, Ge CCRMA Stanford University Stanford CA United States

VVRMA is an interactive, audiovisual, fully immersive VR field trip to a virtual reimagining of CCRMA—Stanford University’s Center for Computer Research in Music and Acoustics. Envisioned as a "VR interactive museum for computer music", VVRMA is the name of the virtual centerpiece building, meticulously modeled after CCRMA’s physical architecture. Within VVRMA, visitors explore various Zones of Interest (ZOIs), which are collections of immersive experiences that thematically mirror various research labs at CCRMA. As design case studies, this paper examines the first two ZOIs: 1) "From Sound to Brain" (a boat ride into the ear canal to learn about the science of hearing), and 2) "The World of Artful Design" (a musical city for exploring interactive audiovisual design and humanistic implications of technology). VVRMA aims to create a playful, expressive, and immersive learning space accessible to a general audience, who are curious about music, technology, and the medium of VR. This paper chronicles the design of VVRMA through the lens of humanistic tool-building, emphasizing programmable audio and VR’s immersive affordances. © 2024, international conference on New Interfaces for Musical Expression. All rights reserved.

关键词： Research laboratories

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FPGA Chip-Based Multi-Module System Verification Methodology 5

FPGA Chip-Based Multi-Module System Verification Methodology

引用

5th international conference on Electronic Engineering and Informatics, ICEEI 2023

作者： Chen, Haojie Zuo, Shikai School of Optical and Communication Engineering Xiamen University of Technology Xiamen China

ISBN: (纸本)9781643685021

This paper proposes a functional verification method for multi-module system field programmable gate array (FPGA) chips. According to the FPGA integrated netlist information, multiple modules to be tested as well as the connection relationship between modules to be tested and the system are all extracted accurately to get a brand-new netlist of modules to be tested. Then the verification excitation is inputted from the outside to verify the extracted netlist, which reduces the compilation time of the large-scale FPGA chip, as well as reduces the configuration time of the chip function verification, accelerates the speed of the simulation, and improves the simulation and verification efficiency. This method has been successfully applied to the FPGA chip circuit function verification engineering practice. © 2024 The Authors.

关键词： field programmable gate arrays (FPGA)

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Implementing Linear Modulation Schemes with field programmable Analog Arrays 15

Implementing Linear Modulation Schemes with Field Programmab...

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15th international conference on Computing Communication and Networking Technologies, ICCCNT 2024

作者： Shadangi, Ashish Ranjan Dastidar, Ananya G.S Sanyal School of Telecommunication Indian Institute of Technology Kharagpur India Bhubaneswar India

ISBN: (纸本)9798350370249

This study utilizes Modern field programmable Analog Arrays (FPAA) technology to showcase the application of various linear modulations, such as Single Sideband (SSB), Double Sideband (DSB), and Double Sideband with Suppressed Carrier (DSB-SC). By utilizing FPAA, many of the challenges associated with traditional DCS kits and discrete component circuit-based linear modulation approaches are circumvented. The FPAA circuits are developed using double sideband modulation techniques tailored to the requirements of analog RF transmission systems. With FPAA devices, which can be tailored based on electrical properties and signal shapes, this suggested solution makes it easier to reconstruct analog conditioning stages. Modulation of a sinusoidal carrier signal includes demodulation, DSB, DSB-SC, and SSB using a multiplier. These structures’ functional elements are built with customisable analog modules (CAMs) from Anadigm Designer 2, specifically AN231E04 and AN220E04 FPAA models. Simulations and experimental results align well with theoretical predictions, demonstrating the efficacy of the approach. Additionally, this paper introduces a new proposal that utilizes the structure of customizable analog blocks (CABs) and the Anadigm Designer2 software to implement DSB and DSB-SC technology. The AN231E04 board by Anadigm Inc. is utilized for system construction and verification. These modulation schemes offer potential for laboratory experimentation and the creation of virtual labs. © 2024 IEEE.

关键词： Religious buildings

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