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检索条件"任意字段=International Conference on Field Programmable Technology"

共 12062 条记录，以下是61-70 订阅

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Magnetic-field-Assisted LCD Stereolithography for Centipede-Inspired Magnetic Soft Robot

Magnetic-Field-Assisted LCD Stereolithography for Centipede-...

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2024 IEEE international conference on Robotics and Biomimetics, ROBIO 2024

作者： Wang, Jinrong Li, Ruixuan Xu, Yaoyuan Li, Shishi Meng, Xianghe Xie, Hui State key Laboratory of Robotics and Systems Harbin Institute of Technology Harbin150080 China

ISBN: (纸本)9781665481090

This paper presents a novel magnetic-field-assisted LCD stereolithography technique for fabricating centipede-inspired magnetic soft robots. Unlike previous DLP-based methods, our approach leverages Liquid Crystal Display (LCD) technology, offering a simpler optical path, comparable resolution, and cost-effectiveness. The method integrates LCD photo-polymerization with a permanent magnet orienting system possessing 5-DOF in motion, enabling precise control over the direction of magnetization patterns during manufacturing. We demonstrate the technique by designing and fabricating a biomimetic centipede robot with programmable deformation capabilities. Finite element analysis was used to simulate the robot's deformation behavior, which was subsequently validated through experimental locomotion tests. The fabricated robot exhibited complex deformation and efficient locomotion in response to external magnetic fields. This approach advances the creation of intricate magnetic arrangements for planar soft robots, potentially expanding their application in fields such as biomedicine and microfluidics. The proposed method provides a new pathway for manufacturing biologically inspired magnetic soft robots with complex programmable behaviors. © 2024 IEEE.

关键词： Liquid crystal displays

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Quantifying Power, Energy and Temperature Variations in Different Multiplexer Designs: A Comparative Approach 1

Quantifying Power, Energy and Temperature Variations in Diff...

引用

1st international conference on Innovative Sustainable Technologies for Energy, Mechatronics and Smart Systems, ISTEMS 2024

作者： Singh, Gurdeep Kaur, Amanpreet Chitkara University Institute of Engineering and Technology Chitkara University Punjab India

ISBN: (纸本)9798350384246

In light of the worldwide energy crisis, this research investigates methods for reducing the power consumption of digital circuits, focusing specifically on multiplexer design using FPGA families. In order to lower power consumption without compromising quality, this article looks at FPGA layouts and synthesis methods. Through the use of technology mapping significant power savings are accomplished without sacrificing function. In order to address the energy limitation challenges, this article offers practical methods for lowering power consumption in FPGA-based devices. © 2024 IEEE.

关键词： field programmable gate arrays (FPGA)

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FPGA Implementation of High-Speed Accelerators for CNN Architecture Using 3D Systolic Array Architecture

FPGA Implementation of High-Speed Accelerators for CNN Archi...

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2024 international conference on Distributed Systems, Computer Networks and Cybersecurity, ICDSCNC 2024

作者： Venkatachalapathy, M.V. Venkateshappa Cyril Prasanna Raj, P. Reva University School of Electronics and Communication Engineering Bengaluru India Cambridge Institute of Technology Department of Electronics and Communication Engineering Bengaluru India

ISBN: (数字)9798350375442

ISBN: (纸本)9798350375442

Convolution Neural Networks (CNNs) are pivotal in image processing. Prominent CNN models include SqueezeNet, MobileNet, Xception, VGG-16, and AlexNet. These models transform 2D data to 1D, emphasizing maximum intensity pixels for data flattening. Traditional systolic arrays are primarily linear and 2D;however, advancements in VLSI and packing technology have increased interest in 3D systolic architectures. This study proposes a 3D systolic architecture where input data is arranged on the X-Y plane, and filter coefficients are fed through the Z-X plane. The architecture utilizes multiplexers, multipliers, adders, 2:1 muxes, and delay registers. The model was developed using MATLAB and verified through HDL simulation on a field-programmable Gate-Array (FPGA). The 3D systolic architecture demonstrated an increase in area and operating frequency compared to conventional architectures, achieving a maximum frequency of 315 MHz and power dissipation below 5 W. The proposed 3D systolic architecture enhances the efficiency of CNN operations, offering a reusable subsystem for complex computations. © 2024 IEEE.

关键词： field programmable gate arrays (FPGA)

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field programmable Gate Array: An Extensive Review, Recent Trends, Challenges and Applications 18

Field Programmable Gate Array: An Extensive Review, Recent T...

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18th INDIAcom;11th international conference on Computing for Sustainable Global Development, INDIACom 2024

作者： Badhoutiya, Arti Jaffer, Zainb Hussein, Heba Mohammed Juyal, Ashima Mittal, Manisha Anand, Rohit Gla University Department of Electrical Engineering Mathura India Al-Farahidi University Medical Technical College Iraq Al-Zahrawi University College Department of Dentistry Karbala Iraq Uttaranchal Institute of Technology Uttaranchal University Department of Ece Dehradun India Gtbit Department of Ece New Delhi India New Delhi India

ISBN: (纸本)9789380544519

A field programmable gate array (FPGA) is a type of programmable logic device that the consumer can modify after production to carry out a variety of tasks, from fundamental logic gate operations to AI systems and beyond. More than 70,000 documents pertaining to FPGA have been found in the two most prominent scientific databases, Scopus and Clarivate Web of Science. These articles demonstrate the wide variety of FPGA-based applications, from navigation systems on Mars rovers to a new mechanism that allows the kilograms redefinition's magnetic suspension system. This paper provides a comprehensive overview of field-programmable gate arrays (FPGAs), taking readers on a journey from the basics to sophisticated programming techniques. No matter how much or how little experience you have with FPGA programming, this study will be an invaluable resource for filling in the gaps in your knowledge. Readers will have a solid grounding in essential topics including FPGA architecture, hardware description languages, and synthesis. The present work addresses critical subjects such as FPGA architecture, hardware description languages, and synthesis, thereby providing readers with a robust foundation. Furthermore, it boldly ventures into the domain of advanced topics, including high-level synthesis and parallel processing, amplifying its appeal to seasoned FPGA enthusiasts. It is unequivocally evident that this work serves as an indispensable resource, equipping individuals from diverse backgrounds with the proficiency to fully exploit the remarkable potential of FPGAs across a myriad of applications and industries. This study also provides an overview of the recent trends and evolution of the related applications. © 2024 Bharati Vidyapeeth, New Delhi.

关键词： advancement component FPDGs performance programming

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In-Flight Logic Analysis on OPS-SAT 17

In-Flight Logic Analysis on OPS-SAT

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17th international conference on Telecommunications (ConTEL)

作者： Henkel, Maximilian Hoermer, Andreas J. Evans, David Wenger, Manuela Graz Univ Technol Inst Commun Networks & Satellite Commun Graz Austria ESA ESOC Adv Concepts & Management Support Off Darmstadt Germany

ISBN: (纸本)9798350302233

Nothing is perfect. Even carefully developed hardware components can sometimes exhibit unexpected behaviour. This is even more likely in harsh environments, like the one satellites are exposed to. However, on satellites hardware analysis is limited to the data obtained by a constrained set of integrated sensors. Therefore, only expected failure cases can be traced, or only indirect monitoring is possible. In this paper, we present an adaptable way to analyse hardware in the field, to solve this problem. Our approach was implemented in-flight on ESA's OPS-SAT satellite, where such an unexplainable fault was noticed. Fortunately, OPS-SAT contains a reconfigurable field-programmable Gate Array (FPGA) allowing a logic analyser functionality to be implemented. Thereby, any signal present in the FPGA fabric becomes traceable, including all externally connected ones. Here, we describe the implementation, its deployment and the successful execution on the OPS-SAT satellite. Using the captured traces, we performed an in-depth analysis of the erroneous behaviour. Our understanding is, that this is the first time such a technique has been implemented on a flying spacecraft. We hope to encourage in-field adoption, especially in-space FPGA reconfiguration, to drive future innovation.

关键词： Logic testing field-programmable gate arrays (FPGA) data buses reconfigurable logic space technology low-earth-orbit (LEO) satellites

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Research on Image Processing System Based on Computer Artificial Intelligence technology 5

Research on Image Processing System Based on Computer Artifi...

引用

5th IEEE international conference on Civil Aviation Safety and Information technology, ICCASIT 2023

作者： Chen, Xin Zhenjiang Vocational Technical College Zhenjiang China

ISBN: (纸本)9798350310603

This paper introduces the two-channel digital image processing technology. The system uses FPGA as its core processing unit. Infrared thermal imager and CCD camera were used for the shooting. The FPGA composed of programmable gate array realizes the pre-processing of the acquired image data and interacts with it. The video image processing of the two channels is completed, and the image features are extracted. Verilog language, built-in DSP core and NiosII processor are used to design the hardware. The experimental results show that this method has good real-time performance, good image processing effect, low cost and simple structure. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

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Enhancing Reliability and Energy Efficiency in Network-on-Chip Architectures through Hybrid Sorting Algorithm-Based Core Mapping 38

Enhancing Reliability and Energy Efficiency in Network-on-Ch...

引用

38th international conference on VLSI Design, VLSID 2025

作者： Reddy, B. Naresh Kumar Jogi, Srinivasulu Krishna, Y. Charan NIT Tiruchirappalli Department of ECE Tiruchirappalli India

ISBN: (纸本)9798331522445

Reliability and energy efficiency are critical challenges in the design of modern Network-on-Chip (NoC) architectures, where the efficient mapping of computational tasks to processing cores plays a pivotal role in overall system performance. To address these challenges, A hybrid sorting algorithm-based core mapping strategy that combines Bitonic and Selection sorters has been proposed. The Bitonic sorter is employed for high-throughput, parallel sorting of task sequences, ensuring an efficient initial task placement. Subsequently, the Selection sorter refines the mapping by focusing on core reliability and energy efficiency, operating in a dual-mode that adapts to varying workload demands. This hybrid approach significantly reduces communication overhead, minimizes energy consumption, and enhances the overall reliability of NoC systems. A field programmable Gate Array (FPGA) was used to measure performance metrics such as application runtime, area, and onchip power consumption. Experimental results using synthetic and real-world benchmarks demonstrate the effectiveness of the proposed algorithm, showcasing its potential to optimize task-to-core mappings for next-generation NoC designs, © 2025 IEEE.

关键词： field programmable gate arrays (FPGA)

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An FPGA-Based Time-to-Digital Converter with Online Calibration Methodology

An FPGA-Based Time-to-Digital Converter with Online Calibrat...

引用

conference on Precision Electromagnetic Measurements (CPEM) / Joint NCSL-international Annual Workshop and Symposium (NCSLI)

作者： Jia, Zhengsen Wang, Yuzhuo Ding, Jie Xu, Qian Zhu, Yadongyang Natl Inst Metrol Beijing 100029 Peoples R China Beijing Inst Petrochem Technol Sch Informat Engn Beijing 102617 Peoples R China

ISBN: (纸本)9798350361056;9798350361049

This paper introduces an effective online compensation mechanism for time-to- digital converters (TDCs) implemented on field-programmable Gate Arrays (FPGAs), which are highly sensitive to process, voltage, and temperature (PVT) variations. The online compensation strategy exploits the synergy between an external high-precision clock signal and the internal chip clock for real-time correction of TDC outputs. Our TDC architecture incorporates a coarse-fine counting scheme, complemented by a start-stop calibration module and a ring oscillator for precise time compensation. The proposed TDC system has been successfully implemented and tested on a Xilinx Artix-7 35T FPGA board. Measurement results demonstrate that our system achieves a minimum time resolution of 18.9 picoseconds (ps) and maintains a root mean square (RMS) resolution within 20 ps, even under temperature variations.

关键词： Time-to-digital Converters (TDCs) field-programmable Gate Arrays (FPGAs) Online Calibration

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A low-cost 4 ps root-mean-square resolution time-todigital converter implemented in a 28 nm field-programmable gate array

A low-cost 4 ps root-mean-square resolution time-todigital c...

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7th international conference on Electronics technology, ICET 2024

作者： Liu, Jinxin Deng, Peipei Liu, Juan Wang, Ying Microsystem and Terahertz Research Center China Academy of Engineering Physics Chengdu China

ISBN: (纸本)9798350363951

This paper presents the implementation of a 28 nm field-programmable gate array (FPGA)-based time-to-digital converter (TDC), which has both high resolution and low-cost characteristics. Due to the simple TDC structure, only a few resources are required, making it suitable for multi-channel applications. An eight-channel TDC was designed in this study. In addition, an automatic nonlinearity calibration logic is implemented within the FPGA, guaranteeing stable performance of the TDC over a wide temperature range. The test results show that the average bin size of a typical channel is 2.55 ps, and the single-shot precision is better than 4 ps. © 2024 IEEE.

关键词： Calibration

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A customized convolutional neural network structure design based on field-programmable Gate Array 7

A customized convolutional neural network structure design b...

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7th international conference on Computer Information Science and Application technology, CISAT 2024

作者： Zhang, Jiahong Yin, Dejun Nanjing University of Science and Technology Nanjing China

ISBN: (纸本)9798350375107

In this paper, different hardware deployment schemes are designed to accelerate the overall reasoning process of convolutional neural network according to the characteristics of large amount of calculation in convolution layer and large amount of parameters in linear layer. For convolutional neural networks with fewer layers, the LUT multiplication circuit is used instead of the DSP multiplication and the parameters are fixed in the circuit to reduce the dependence on DSP and ROM resources. This makes it possible to achieve higher parallelism reasoning on FPGAs with fewer resources. In this paper, a reduced-order convolutional neural network is trained based on the MNIST training set. After 8bit quantization, it is deployed to the FPGA and the inference speed reaches 7.356 us, which is 339 times faster than that of the CPU. © 2024 IEEE.

关键词： Convolutional neural networks

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