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检索条件"任意字段=International Conference on Field Programmable Technology"

共 12062 条记录，以下是81-90 订阅

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The design improvement for hardware configuration method during FPGA loading 4

The design improvement for hardware configuration method dur...

引用

4th international conference on Mechanical Engineering, Intelligent Manufacturing, and Automation technology, MEMAT 2023

作者： Tian, Linyu Yang, Dongliang Huang, Keying Zhao, Jun Xi'an Aeronautics Computing Technique Research Institute AVIC Xi’an710065 China

ISBN: (纸本)9781510674820

Ensuring the safety state of a product is a crucial consideration during system design, especially during transient periods such as power-up when the logic loading process occurs. Poor design in such cases can often lead to false outputs from the product, causing unintended operation of external loads and posing risks. To guarantee that the product meets the safety requirements during power-up transients, this article proposes an improved hardware configuration design during FPGA loading. The effectiveness of the improved design is verified through implementation and validation, and several key points to be noted in subsequent designs are summarized. © 2024 SPIE.

关键词： field programmable gate arrays (FPGA)

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Fast digital filter for frequency discriminator 3

Fast digital filter for frequency discriminator

引用

3rd IEEE international conference on Electronic technology, Communication and Information, ICETCI 2023

作者： Yao, Xinkai Xin, Wei Jin, Yu Li, Meng Guo, Qi Li, Xueyan Beijing University of Chemical Technology College of Information Science and Technology Beijing China Min. of Natural Resources China Aero Geophysical Survey Remote Sensing Center for Natural Resources Key Laboratory of Airborne Geophysics and Remote Sensing Geology Beijing China

ISBN: (纸本)9798350398410

The frequency discriminator is a circuit to detect signal frequency, it is widely used in various high-precision transducer. Frequency discriminators in optically pumped magnetometers (OPM) require fast tracking of the magnetic resonance center frequency, in which a fast-digital filter is necessary. This paper designs a high-speed digital filter, and is verified in field programmable gate array (FPGA). The designed filter is composed of a cascaded integrator-comb (CIC) digital filter and infinite impulse response (IIR), the CIC filter is developed to filter out harmonics and reduce the sampling rate, IIR filter is designed to further filter out high-frequency signals and pick up direct-current(DC)information. Compared with traditional Butterworth filters, the designed IIR filter saves about 40% stabilization time with less resources. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

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An Improved Method for High Speed DUC in Broadband Transmitters 7

An Improved Method for High Speed DUC in Broadband Transmitt...

引用

7th international conference on Electronic Information technology and Computer Engineering (EITCE)

作者： Zhou, Xinxing Wen, Fei Yan, Ming CSSC Res Inst 722 Wuhan 430205 Hubei Peoples R China

ISBN: (纸本)9798400708305

In the modern broadband transmitters, the sampling rate of DAC is required to be higher and higher, the bandwidth of the transmitted signal, meanwhile, is required to be wider and wider. The traditional method of the digital up conversion (DUC) is unable to meet the demand for the broadband transmission because of the limitation of the clock frequency of the field programmable gate array (FPGA). For broadband transmission applications, an improved method of high speed DUC is proposed. The interpolation filtering and direct digital synthesis (DDS) are optimized. Firstly, the mathematical model of high speed DUC is derived, and the structure of the traditional DUC is improved. The efficient and flexible structures of the interpolation filtering and DDS are designed. Secondly, the calculation method of multichannel coefficients of the interpolation filter is given. The calculation method of multichannel phase parameters of parallel DDS is also given. The hardware implementation shows that the proposed method has correct function, and can be applied to engineering conveniently. The data rate of the digital signal at intermediate frequency (IF) output from the hardware can reach 960MSps. The proposed method can realize interpolations with different multiples, and can also generate high speed local oscillator signals with different rates. It can meet the requirements of transmitting wide band and high rate signals in the modern broadband transmitters.

关键词： Digital up conversion High rate Poly phase filtering field programmable gate array

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Study on Voltage Influence on FPGA-Based Time-to-Digital Converters

Study on Voltage Influence on FPGA-Based Time-to-Digital Con...

引用

IEEE international Instrumentation and Measurement technology conference (I2MTC) - Rising Above Covid-19

作者： Xu, Xinchi Wang, Yonggang Univ Sci & Technol China Dept Modern Phys Hefei Peoples R China

ISBN: (纸本)9781665453837

field programmable gate arrays (FPGAs) based time- to-digital converters (TDCs) have been broadly investigated and widely used in recent years. However, voltage variations on the power distribution network (PDN) of FPGA are significantly affecting and sometimes devastating to the TDC performance. In this paper, we experimentally measure the performance changes of the tapped delay line (TDL) based TDC under conditions that the PDN has static and transient voltage variations and analyze the voltage influences theoretically. The test results show 0.2%/mV degradation of the TDC resolution with voltage drop and 12%/mV deterioration of the average RMS precision with voltage deviation from typical. Besides, performance degradation due to transient voltage fluctuations caused by switching activities of adjacent digital circuits is also experimentally demonstrated. In particular, the RMS precision exhibits periodic deterioration with the measured time interval, which can be reasonably explained in theory. For the influence coming from static voltage variations, we find the performance change can be greatly suppressed by the dynamic calibration method. However, for the influence coming from voltage transients, the performance degradation is inevitable, which raises a warning for FPGA management, especially for multi-tenant FPGAs where multiple untrusting cloud users simultaneously reside in a single FPGA. The test results and theoretical analysis in this paper can guide system optimization and real-time correction to reduce the impact of voltage transients.

关键词： field programmable gate array time-to-digital converter voltage variations

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Design of parking assist system based on FPGA 3

Design of parking assist system based on FPGA

引用

3rd international conference on Electronic Information Engineering and Data Processing, EIEDP 2024

作者： Zhang, Xiaoxu Shan, Dan Li, Henan Dalian Neusoft University of Information Dalian China

ISBN: (纸本)9781510680531

With the development of electronic information technology, image processing technology has been widely applied in various fields, and parking assistance systems are one of them. This article proposes a design scheme for a parking assistance system based on FPGA. The system collects image information through a camera, identifies landmarks in the image, calculates distance based on ultrasonic sensor detection results, and draws reverse warning lines. The system uses OSD technology to overlay image watermarks and achieve dynamic parking images. After experimental testing, the system can accurately measure distance, correctly draw parking prompt lines, and display them on the system screen, assisting the driver in real-time parking. This system will be widely applied in fields such as intelligent driving and autonomous driving. © 2024 SPIE.

关键词： field programmable gate arrays (FPGA)

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FPGA-based Train Onboard PCIe Board Design and Implementation 3

FPGA-based Train Onboard PCIe Board Design and Implementatio...

引用

3rd international conference on Electrical Engineering and Mechatronics technology, ICEEMT 2023

作者： Chen, Xiao Qi Zhang, Li Yan Li, Chang Xian Dalian Jiaotong University School of Automation and Electrical Engineering Dalain China Dalian Jiaotong University School of Computer and Communication Engineering Dalian China Dalian Jiaotong University National and Local Joint Engineering Research Center for Rail Transit Equipment Dalain China

ISBN: (纸本)9798350303698

Since its introduction in 1992, PCI (Peripheral Component Interconnect) interface has been widely applied in various fields. In 2001, Intel launched the PCIe (Peripheral Component Interconnect Express) interface, which aimed to replace the old PCI, PCI-X (Peripheral Component Interconnect eXtended) and AGP (Accelerated Graphics Port) bus standards. PCI-Express interface features high speed and high bandwidth, which overcomes the bottlenecks of traditional PCI bus in system bandwidth and speed and demonstrates a promising application potential. By using FPGA (field programmable Gate Array) to design data transmission based on PCIe bus, the hardware design cost can be reduced, the integration can be improved, and the flexibility and adaptability of the design can be enhanced by using the programmable features of FPGA. In this paper, a transmission scheme of PCIe Hard IP Core and DMA (Direct Memory Access) IP Core based on Altera FPGA is implemented, and the design implementation and data transmission test are conducted. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

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Advanced Encryption Standard-128 bit Design Flow for ZYNQ-7 ZC702 Evaluation Board 3

Advanced Encryption Standard-128 bit Design Flow for ZYNQ-7 ...

引用

3rd international conference on Artificial Intelligence and Smart Energy, ICAIS 2023

作者： Nisha, B. Muthu Nithya, V. Selvakumar, J. Srm Institute of Science and Technology Department of Ece Kattankulathur India

ISBN: (纸本)9781665462167

The study of cryptography techniques on field programmable Gate Array needs extensive research attention. Evaluation Boards is one such area of hardware security measures. An encryption algorithm must be developed on a specific family board. The Advanced Encryption Standard 128-bit algorithm is proposed in this study for the ZYNQ family board. Particularly, the ZYNQ-7 ZC702 Evaluation Board. Then, its parameters are appropriate for top-down encryption algorithms. The results of the algorithm are generated as reports on Register Transfer Logic (RTL) and look-up table usage. This study provides recommendations for the future in terms of data security on hardware. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

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Research on Lens-Coupled Dual-Channel Single-Channel Single-Photon Detector System 21

Research on Lens-Coupled Dual-Channel Single-Channel Single-...

引用

21st international conference on Optical Communications and Networks, ICOCN 2023

作者： Wu, Wankang Feng, Guilan Zhao, Tianqi Lin, Chunlan Pan, Jinlv Li, Jiabao China Jiliang University Hangzhou China

ISBN: (纸本)9798350343502

关键词： field programmable gate arrays (FPGA)

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Realization of Parallel Distributed Temperature Sensor Network Based on field programmable Gate Array 5

Realization of Parallel Distributed Temperature Sensor Netwo...

引用

5th international conference on Electronic Engineering and Informatics, EEI 2023

作者： You, Binyu Feng, Shiwei Yao, Zhanwu Lv, Xianliang Wang, Yaning Zhou, Yinqi Beijing University of Technology Chaoyang District Beijing China China Electronics Standardization Institute China

ISBN: (纸本)9798350327076

The digital temperature sensor based on the logic resources of the FPGA can monitor the global temperature of the field programmable Array (FPGA) in real time. This paper implements this temperature sensing network on a Xilinx XC7Z020 FPGA in 28 nm process, which uses a logic consumption of 384, occupying only 0.7% of the total Look-Up-Tables (LUTs). A single sampling time is 60 μs, which ensures data reliability and stability. The total on-chip power consumption of the system is approximately 5 W, and the realization of the distributed temperature measurement network is realized under the condition of small power consumption and resource occupation. © 2023 IEEE.

关键词： Electric power utilization

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FPGA Implementation of Stochastic Approximate Multipliers for Neural Networks 1

FPGA Implementation of Stochastic Approximate Multipliers fo...

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1st international conference on Electronics, Communication and Signal Processing, ICECSP 2024

作者： Saravanan, V. Dayana, R. Thillai Rani, M. Sudha, M. Varun, M. Rosi, A. Saveetha School of Engineering Saveetha Institute of Medical and Technical Sciences Department of Nano Electronics Materials and Sensors Tamilnadu Chennai India SRM Institute of Science and Technology Vadapalani Campus Department of CSE Tamilnadu Chennai India Sri Krishna College of Technology Department of ECE Coimbatore Tamilnadu Chennai India SNS College of Engineering Department of ECE Tamil Nadu Coimbatore India Chennai Institute of Technoloy Department of ECE KundrathoorTamilnadu Chennai India Vel Tech Rangarajan Dr. Sagunthala R and D Institute of Science and Technology Department of ECE Chennai Tamil Nadu Avadi India

ISBN: (纸本)9798350364590

In the age of edge computing, tiny and efficient neural network (NN) architectures are in high demand. Existing deterministic multipliers in neural networks suffer from high power consumption and space overheads. The research presents a novel field-programmable Gate Array (FPGA) implementation of stochastic approximate multipliers (SAMs) to improve NN performance. SAMs are ideal for areas with limited resources, such as edge devices, since their components take up less space and consume less power. The technique utilizes SAMs' stochastic nature to lower power and space needs while preserving NN accuracy. The study includes detailed descriptions of the SAM architecture, hardware integration, training methodologies, FPGA implementation, and performance assessments. The proposed system, with inference rates of 8.6 ms and an accuracy of 97.5%, consumes 15.6 kWh of total energy, compared to the existing system's 22.1 kWh. The efficiency of the SAM-based FPGA NN architecture is demonstrated by decreased logic and memory usage, faster inference times, and improved accuracy retention. The results open up possibilities for the employment of energy-efficient, high-performance NNs in mobile and edge computing applications. © 2024 IEEE.

关键词： field programmable gate arrays (FPGA)

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