This paper presents a feedback circuit topologies based on AlGaN/GaN (Aluminum Gallium Nitride / Gallium Nitride) MIS-HEMT (Metal Insulator Semiconductor High Electron Mobility Transistor) to address the issue of abno...
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ISBN:
(纸本)9798331517137;9798331517144
This paper presents a feedback circuit topologies based on AlGaN/GaN (Aluminum Gallium Nitride / Gallium Nitride) MIS-HEMT (Metal Insulator Semiconductor High Electron Mobility Transistor) to address the issue of abnormal output ripple in DC-DC buck converters and mitigate voltage overcharge at the operating point. The proposed circuit structure is simulated and calibrated using the ADS (Advanced design System) platform. Subsequently, the circuit's output characteristics and principles of the optimized bootstrap comparator are analyzed. The results show that the maximum output voltage fluctuation is 0.05 V and the average fluctuation is less than 0.5 %, providing references and suggestions for the feasibility and application potential of the buck converter circuit structure in monolithic integrated GaN power converters.
The demands for near-infrared (NIR) image sensors keep increasing for camera applications. For high sensitivity in NIR imaging, RGBW color filter array is used with the white color filter adapted for the infrared pixe...
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ISBN:
(纸本)9798331517137;9798331517144
The demands for near-infrared (NIR) image sensors keep increasing for camera applications. For high sensitivity in NIR imaging, RGBW color filter array is used with the white color filter adapted for the infrared pixel. However, the crosstalk also increases with high sensitivity. Crosstalk is one of the important optical performance, especially affecting modulation transfer function (MTF). In this paper, the crosstalk is studied and reduced by a NIR-cutoff layer. By optical simulation, the crosstalk in each of the R, G, and B pixels is reduced by about 10%. The overall crosstalk in the pixels was reduced from 75.5% to 48.2%. Therefore, this paper shows that the crosstalk at NIR wavelengths is improved while maintaining the high sensitivity characteristics of RGBW CFA image sensors.
The reliability of design, process, inner microstructure and material used in integratedcircuit is the key to determining the inherent reliability level of the device itself. With the continuous updating and iteratio...
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ISBN:
(纸本)9798350353808
The reliability of design, process, inner microstructure and material used in integratedcircuit is the key to determining the inherent reliability level of the device itself. With the continuous updating and iteration of integratedcircuit manufacturing processes, the size of process microstructure is getting smaller and the integration degree is getting higher. As a result, issues related to circuitdesign layout, manufacturing process, packaging process, and material reliability have gradually become key influencing factors affecting the reliability level of integratedcircuits themselves. How to conduct quality inspection and reliability evaluation on newly developed integratedcircuits, effectively identify defects and weak links that affect device quality and application reliability, and fully verify the true reliability level of devices, has very important practical significance. This study proposes a reliability risk based integratedcircuit microstructure evaluation method, which analyzes the key elements that affect device reliability in advance and establishes corresponding testing and evaluation items. Through physical testing and verification of the device, the real reliability risks of the device can be identified and provide a basis for device design, process improvement, selection, and application design. This method aims to provide integratedcircuit users with an effective means of quality inspection and reliability evaluation to ensure the inherent reliability of microelectronic devices.
The ion-sensitive field effect transistors (ISFETs) with direct ionic solution gate (DG) and an extended gate (EG) are fabricated for electrophysiology detection. Backgate modulation is employed to adjust the operatio...
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ISBN:
(纸本)9798331517137;9798331517144
The ion-sensitive field effect transistors (ISFETs) with direct ionic solution gate (DG) and an extended gate (EG) are fabricated for electrophysiology detection. Backgate modulation is employed to adjust the operation point of ISFETs, thereby achieving enhanced sensitivity during operation. It has been determined that the charging mechanisms of the electric double layer (EDL) between ion liquids and solids are a key determinant of sensitivity. In this case, ensuring direct contact between the ionic liquid and the oxide film, rather than using an extended gate, is crucial for fabricating high-performance ISFETs.
This paper presented a transient-enhanced low dropout voltage (LDO) regulator with an integrated push- pull composite power transistor and an embedded voltage reference (VR). The use of a composite power transistor sh...
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ISBN:
(纸本)9798331517137;9798331517144
This paper presented a transient-enhanced low dropout voltage (LDO) regulator with an integrated push- pull composite power transistor and an embedded voltage reference (VR). The use of a composite power transistor shifts parasitic poles to higher frequencies, enhancing stability. A recycling folded cascode (RFC) amplifier achieves higher loop gain, improving load and line regulation. A recovery time enhancement circuit reduces overshoot recovery. The VR employs various resistor types for high-order compensation, with trimming ensuring stable performance across corners. Implemented in GF 55nm technology, the LDO operates at 1V to 1.2V input voltage, delivering up to 50mA current with less than 200mV dropout. It consumes 43.85 mu A quiescent current, settles within 1 mu A, and exhibits excellent line regulation (3.76mV/V), load regulation (0.0076mA/mV), and PSRR (-44dB @ 1KHz).
This work presents the design of a low noise amplifier (LNA) using TSMC CMOS 28-nm technology, capable of operating at an ultra-low voltage of 0.2 V with a minimum power consumption of 48 mu W. The LNA achieves a gain...
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ISBN:
(纸本)9798331517137;9798331517144
This work presents the design of a low noise amplifier (LNA) using TSMC CMOS 28-nm technology, capable of operating at an ultra-low voltage of 0.2 V with a minimum power consumption of 48 mu W. The LNA achieves a gain ranging from 11.3 dB to 29.3 dB while maintaining input and output return losses below -10 dB. At maximum gain, the LNA achieves a NF of 1.93 dB. Furthermore, an optimized performance mode offers power consumption below 100 mu W, with other performance metrics remaining competitive.
This article presents a high efficiency power amplifier (PA) based on TSMC 28 nm complementary metal oxide semiconductor (CMOS) process at 2.4 GHz. The transistors in the proposed amplifier are biased at different sta...
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ISBN:
(纸本)9798331517137;9798331517144
This article presents a high efficiency power amplifier (PA) based on TSMC 28 nm complementary metal oxide semiconductor (CMOS) process at 2.4 GHz. The transistors in the proposed amplifier are biased at different states to enhance both the linearity and power added efficiency (PAE). The PA's saturation output is 25.6 dBm and it gets a maximum output of 23.7 dBm at output 1 dB compression point (OP1dB). The PAE achieved 41% at the OP1dB point.
A Low-Voltage Low-Power (LVLP) scalable voltage reference without the use of the parasitic vertical PNP, based on Two Transistor (2T) bandgap core is proposed. The voltage reference is achieved through Global Foundry ...
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ISBN:
(纸本)9798331517137;9798331517144
A Low-Voltage Low-Power (LVLP) scalable voltage reference without the use of the parasitic vertical PNP, based on Two Transistor (2T) bandgap core is proposed. The voltage reference is achieved through Global Foundry (GF) 55 nm CMOS technology, the minimum power supply can be lowered to 0.55V. At the nominal supply voltage 0.9V, the temperature coefficient of the proposed voltage reference is 1.837ppm/degrees C with 0.17%-line sensitivity and -66.24dB power supply rejection (PSR). By using extremely large resistance, at the minimum supply voltage 0.5V the power consumption 16.35nW.
The design of impedance matching networks is a crucial part in the mm-wave integratedcircuit. There are two ways to model passive networks: discrete network model and global network model. The accuracy of the former ...
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ISBN:
(纸本)9798350389968
The design of impedance matching networks is a crucial part in the mm-wave integratedcircuit. There are two ways to model passive networks: discrete network model and global network model. The accuracy of the former is not high enough, especially in mm-wave, and the sampling number of the latter is too large. A new fine-tuning model of passive networks is proposed to solve this problem, which has enough precision and less sample size. An automatic design example of impedance matching network using this model proves the model is effective.
In this paper, a fully integrated 2.4 GHz high-linearity class E power amplifier (PA) is proposed based on the TSMC 28 nm CMOS process. By optimizing the topology of the design, balance between linearity and efficienc...
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ISBN:
(纸本)9798331517137;9798331517144
In this paper, a fully integrated 2.4 GHz high-linearity class E power amplifier (PA) is proposed based on the TSMC 28 nm CMOS process. By optimizing the topology of the design, balance between linearity and efficiency, as well as reducing power consumption is achieved under the condition of low voltage power supply. The proposed power amplifier adopts the differential topology with two-stage linear power amplifier driving a class E power amplifier. By utilizing the source inductance and series resistance, the stability of the PA is improved. Finally, the proposed PA achieves saturation output power (Psat) of 18.53 dBm, gain of 24.52 dB, output 1 dB compression point (OP1dB) of 17.17 dBm, maximum power added efficiency (PAE) of 48.96%, and 37.38% at the OP1dB point. The area of the layout is 1959 mu m x 726 mu m.
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