In response to the optimization design of the matching circuit of piezoelectric ultrasonic transducers, this paper takes battery powered small integrated soar as an example to explore the optimization design method of...
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Formal verification methods can prove whether a integratedcircuit(IC) design satisfies desired properties with higher verification efficiency than traditional testing methods. However, it requires manual specificatio...
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The small signal modeling, design, fabrication, and measurement about monolithic millimeter-wave integratedcircuit (MMIC) using gallium nitride (GaN) power amplifier (PA) on silicon carbide (SiC) working at the E ban...
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The small signal modeling, design, fabrication, and measurement about monolithic millimeter-wave integratedcircuit (MMIC) using gallium nitride (GaN) power amplifier (PA) on silicon carbide (SiC) working at the E band are proposed in this paper. The two stage PA used customized 4 x 75 mu m transistor with 100 nm T gate technology. The extraction and optimization of small signal model are based on single GaN high electron mobility transistor (HEMT)'s measurement. Balanced structure and new method are used by low impedance matching, which can simplify circuits prominently and benefit for die size reduction. Radial stub and LC stub are made the whole circuit in absolute stable status;the in-series DC block metal-insulator-metal capacitor from the matching circuit ensure the process is within small tolerances. From the 61-66 GHz bandwidth, a peak 10.7 dB small signal gain is obtained from the designed MMIC GaN PA, and also, the maximum output power can reach 29.7 to 30.4 dBm from 61 to 66 GHz, with an associated the peak drain efficiency of 18.8%. The final die size without dicing slot is 3.0 x 1.74 mm2. A novel E band power amplifier monolithic millimeter-wave integratedcircuit (MMIC) using 100 nm T-Gate gallium nitride HEMT on silicon carbide is proposed in this paper. New matching, circuit stability, and small tolerances in process optimization methods are used for this MMIC, and finally, good measurement results verify the ***
The Von Neumann structure is the most applied structure in modern computers. However, it is hitting the bottleneck due to higher fabrication requirements and more demanding high-performance equipment demands. Meanwhil...
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ISBN:
(纸本)9798331517137;9798331517144
The Von Neumann structure is the most applied structure in modern computers. However, it is hitting the bottleneck due to higher fabrication requirements and more demanding high-performance equipment demands. Meanwhile, neuromorphic computing, a life science-inspired structure, is in booming development. In addition, the "Spike Neural Network" (SNN) of the 3rd generation, whose mechanism includes Spike-Timing Dependent Plasticity (STDP) is also flourishing as a subsequent derivative. In this project, a circuit for the STDP hardware implementation is achieved and optimized. We use the self-developed neuro synaptic unit to preprocess the data to achieve a more efficient and accurate conversion of pixels into analog signals sent to the neural network circuit. The project successfully implemented an ideal memristor model in software for simulation. The weight gain and weight reduction circuitry were also designed and revised based on previous releases, eventually achieving the desired adjustable STDP performance and improved power consumption. The functionality of the STDP circuit is validated by successfully adjusting the memristor conductance based on the spike timing. Finally, a 4x2 array is created, and a simple image identification task is completed. The array has good robustness to image distortion. In the future, the array structure will be designed in the 1T1R scheme for the VLSI implementation, and the peripheral circuits will be further optimized.
This paper reviews recent work on the acceleration of static timing analysis (STA), with a special focus on parallel and heterogeneous computing techniques. Timing analysis is one of the most critical tasks in circuit...
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To further enrich the experimental content of the Electronic Engineering Training course, a design scheme for a radio circuit based on the FT6088 chip is specifically proposed. The paper delves deep into the design ar...
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This Special Section of IEEE Journal of Solidstate circuits (JSSC) highlights outstanding papers presented at the 2023 IEEE international Solid-State circuits conference (ISSCC), which was held from February 19 to 23,...
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This Special Section of IEEE Journal of Solidstate circuits (JSSC) highlights outstanding papers presented at the 2023 IEEE international Solid-State circuits conference (ISSCC), which was held from February 19 to 23, 2023, in San Francisco, USA, under the conference theme “Building on 70 years of Innovation in Solid-State circuitdesign.” ISSCC is the foremost global forum for the presentation of advances in solid-state circuits and systems-on-a-chip and offers a unique opportunity for engineers working at the cutting edge of integratedcircuit (IC) design and application. The conference includes several technical programs ranging from analog to mixed-mode, digital, RF, and power management circuits and systems with applications in a wide variety of fields. This JSSC Special Section highlights selected papers from ISSCC particularly on topics related to the Imagers, MEMS, Medical, and Displays (IMMD), and technology Directions (TD) technical programs.
This paper proposes a germanium-silicon integrated low-noise amplifier based on an AC-coupled common-emitter topology by simulation. The circuit structure adopts a cascaded dual-bias circuit pattern, ensuring uncondit...
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ISBN:
(纸本)9798350389968
This paper proposes a germanium-silicon integrated low-noise amplifier based on an AC-coupled common-emitter topology by simulation. The circuit structure adopts a cascaded dual-bias circuit pattern, ensuring unconditional stability of the internal two-port network and demonstrating excellent stability. This design fully showcases the advantages of the common-emitter topology in low-noise amplifier design. Utilizing the ADS electromagnetic simulation software, we successfully designed a seven-stage LNA operating in the frequency range of 200 to 240GHz. Simulation results indicate that at 220GHz, the small-signal gain reaches 23dB, the noise figure is 8.8dB, and both input and output reflection coefficients are below -10dB. The 3dB bandwidth is 20GHz (210-230GHz), confirming the effectiveness of the design.
This paper reviews the state-of-the-art technology, circuit architectures, and design strategies commonly used in high-voltage integratedcircuits. After a brief discussion about the available technologies and devices...
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ISBN:
(纸本)9798350394061
This paper reviews the state-of-the-art technology, circuit architectures, and design strategies commonly used in high-voltage integratedcircuits. After a brief discussion about the available technologies and devices, fundamental analog building blocks used in high-voltage applications are introduced. A novel self-protected input stage and various high-voltage tolerant output stages are reviewed. Finally, industry standard high-voltage comparator and amplifier design examples are given.
DC Solid State circuit Breaker(SSCB) have broad application prospects due to their arc-free operation, rapid interruption capabilities, and exceptionally long lifespans. Building upon traditional DCSSCBs, this paper p...
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ISBN:
(纸本)9798350388954;9798350388947
DC Solid State circuit Breaker(SSCB) have broad application prospects due to their arc-free operation, rapid interruption capabilities, and exceptionally long lifespans. Building upon traditional DCSSCBs, this paper proposes an integrated DCSSCB technology based on silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs), which combines detection and current-limiting functions. The current-limiting unit can effectively suppress instantaneous high-current surges, enhancing the short- circuit withstand time of the DCSSCB and significantly extending its operational lifespan. The detection module operates without sensors, reducing the delay time during interruption. Additionally, the integration of the detection module and the current-limiting module minimizes the overall size of the circuit breaker. The proposed DCSSCB topology was modeled using simulation software, and the impact of various circuit parameters on interruption performance was analyzed. Finally, under 500V/50A conditions, the interruption process during a load short-circuit fault was simulated. The results show that the proposed topology effectively suppresses transient load over-voltages, limits the short-circuit current to approximately 180 A, and achieves a total short-circuit fault clearing time of less than 8 mu s, thereby validating the speed and feasibility of the proposed DCSSCB.
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