We describe a smart-pixel based general purpose parallel processor. Arrays of programmable processing elements and vertical cavity surface-emitting lasers are interconnected in free-space by a compact GRIN rod imaging...
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We describe a smart-pixel based general purpose parallel processor. Arrays of programmable processing elements and vertical cavity surface-emitting lasers are interconnected in free-space by a compact GRIN rod imaging system. A phase modulating liquid crystal spatial light modulator is used to dynamically reconfigure the interconnections. Issues of algorithm design and performance are discussed in the context of a reconfigurable architecture.
Two-dimensional(2-D) paralleloptical data link based upon optical space-CDMA is implemented and experimentally demonstrate, for the first time to the authors' knowledge. In the experiment, the encoded bit-planes ...
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Two-dimensional(2-D) paralleloptical data link based upon optical space-CDMA is implemented and experimentally demonstrate, for the first time to the authors' knowledge. In the experiment, the encoded bit-planes are spatially multiplexed, and it is transmitted through a 16 m-long image fiber having 3×104 pixels. Each input 4×4 bit-plane is optically encoded by an 8×8 2-D optical orthogonal signature pattern. Each receiver can properly recover the intended input bit-plane via the optical decoding process. This result will encourage the application of optical space-CDMA to future high-throughput 2-D parallel data links connecting massivelyparallel processors.
To efficiently exploit the potential of future massivelyparallel and fine-grained optoelectronic processors well-adapted low-level algorithms have to be developed. So called bit and CORDIC algorithms are well suited ...
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To efficiently exploit the potential of future massivelyparallel and fine-grained optoelectronic processors well-adapted low-level algorithms have to be developed. So called bit and CORDIC algorithms are well suited for that purpose. We present a concept for an optoelectronic 3D processor based on this particular algorithm class. This processor allows a hard-wired execution of 8 complex functions like logarithm, exponential function, sine, cosine, arc tangent, square root, multiplication and division without using sophisticated multiplication units. The strength of the 3D processor is based on lots of off-chip interconnections as it is a aspired in smart pixel systems usingoptical I/O arrays. We compared different smart pixel architectures based on bit serial and bit parallel approaches as well as a redundant number representation. All approaches showed nearly the same throughput, whereas the redundant approach offers the best latency. Furthermore, the requirements for the electronic logic and the optical interconnection scheme are specified.
A concept for a future integer arithmetic unit as well as a first implementation of the arithmetic unit's core as smart pixel detector chip is presented. This architecture is well-suited for a realization with 3-D...
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ISBN:
(纸本)0818685727
A concept for a future integer arithmetic unit as well as a first implementation of the arithmetic unit's core as smart pixel detector chip is presented. This architecture is well-suited for a realization with 3-D optoelectronic very large scale integrated (VLSI) circuits. Due to the use of opticalinterconnections running vertically to the circuit's surface no pin limitation is given. This allows massivelyparallelism and a higher throughput performance than in all-electronic solutions. To exploit the potential of opticalinterconnections in VLSI systems efficiently well-adapted low-level algorithms and architectures have to be developed. This is demonstrated for a pipelined arithmetic unit using a redundant number representation. A gate layout for the optoelectronic circuits is given as well as a specification for the necessary optical interconnection scheme linking the circuits with free-space optics. It is shown that the throughput can be increased by a factor of 10 to 50 compared to current all-electronic processors by considering state-of-the-art optical and optoelectronic technolgy.
The major challenge of optical interconnects will be to provide high burst rates while achieving a similar to or better latency than, traditional bit-parallel I/O. Free space optics has the biggest potential. The need...
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The major challenge of optical interconnects will be to provide high burst rates while achieving a similar to or better latency than, traditional bit-parallel I/O. Free space optics has the biggest potential. The need to align each individual bit on its detector will, however, always be a drawback for free space interconnects. For less ambitious implementations, wavelength division multiplexing (WDM) is probably the most promising technology. It can be used to transmit 128 bits or more from a single channel in parallel on a single waveguide. The real advantage of using WDM to traditional bit-parallel I/O, however, is the reduction in faulty products at manufacturing time due to a reduction in physical connections.
This paper describes a VCSEL/Si smart pixel array technology developed at the University of Colorado, and reports on an optoelectronic processor that is based on these hybrid SPAs. This effort is unique in the process...
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This paper describes a VCSEL/Si smart pixel array technology developed at the University of Colorado, and reports on an optoelectronic processor that is based on these hybrid SPAs. This effort is unique in the processing complexity of the pixels, in the bi-directionality of the optical interconnects, and in the thermosonic bonding of the VCSEL and silicon chips.
We experimentally demonstrate four-channel multiplexing of 64-bit (8 x 8) two-dimensional (2-D) parallel data links on the basis of optical space-code-division multiple access (CDMA) by using new modules of optical sp...
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We experimentally demonstrate four-channel multiplexing of 64-bit (8 x 8) two-dimensional (2-D) parallel data links on the basis of optical space-code-division multiple access (CDMA) by using new modules of optical spatial encoders and a decoder with a new high-contrast 9-m-long image fiber with 3 x 10(4) cores. Each 8 x 8 bit plane (64-bit parallel data) is optically encoded with an 8 x 8, 2-D optical orthogonal signature pattern. The encoded bit planes are spatially multiplexed and transmitted through an image fiber. A receiver can recover the intended input bit plane by means of an optical decoding process. This result should encourage the application of optical space-CDMA to future high-throughput 2-D parallel data links connecting massivelyparallel processors. (C) 1998 optical Society of America.
massivelyparallelprocessing is an important way to develop the high performance computer in nowadays;and the optical interconnection is also widely followed with interest in the computer area for its advantages. In ...
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massivelyparallelprocessing is an important way to develop the high performance computer in nowadays;and the optical interconnection is also widely followed with interest in the computer area for its advantages. In this paper, the optoelectronic hybrid parallel multi-processor system (PMPS) developed in our laboratory is an attempt at usingoptical interconnection in order to solve the complex communication problem in the interconnection network of PMPS. Based on the model of communication sequential processes (CSP) a new architecture has been developed, in which there are two multi-processor array layers;One of them is only for computation, the other for communication only between the processors in the first layer. The PMPS greatly improves the communication performance and releases the difficulties of system configuration by means of programs, and therefore, the user could have a friendly interface.
In last year's MPPOI, Gravenstreter and Melhem presented optimal embeddings of ring and torus communications on the POPS architecture, for the case where the number of nodes (n) and the optical Passive Star (OPS) ...
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ISBN:
(纸本)0818675918
In last year's MPPOI, Gravenstreter and Melhem presented optimal embeddings of ring and torus communications on the POPS architecture, for the case where the number of nodes (n) and the optical Passive Star (OPS) coupler degree (d) are powers of two. In the same conference, Bourdin, Ferreira and Marcus proposed stack-graphs as a good model for OPS-based architectures. In this paper we show that directed stack-complete graphs with loops (stack-K-n(+) for short) perfectly model POPS. As a consequence, we settle the question with respect to ring embeddings, presenting optimal embeddings for all values of n and d, based on Euler tours on K-n(+). We also show how to optimally embed de Bruijn (B (g, D)) communications on POPS when g is the number of groups in the POPS topology, using the fact that K-g(+) is also a B (g, 1).
In this paper we describe a problem that arises in mapping process graphs onto a certain communication architecture. The problem is called Bounded p-Contractability. We have shown in earlier work that the problem is N...
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In this paper we describe a problem that arises in mapping process graphs onto a certain communication architecture. The problem is called Bounded p-Contractability. We have shown in earlier work that the problem is NP-complete. In this paper we present two results. The first is a result on a corresponding approximation problem. The second is a heuristic for the problem based on local search. The heuristic is compared with an existing heuristic for the problem.
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