We present the design of a parallel high-performance chipset for computing 1-D complex fast Fourier transforms (FFTs). The chipset is composed of two chips - a photonic FFT processing engine (PFFT) and a photonic data...
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We present the design of a parallel high-performance chipset for computing 1-D complex fast Fourier transforms (FFTs). The chipset is composed of two chips - a photonic FFT processing engine (PFFT) and a photonic data storage element (PRAM). using this chipset, a number of high-speed systems can be created. The chipset is compatible with a number of available interconnect technologies, such as free-space optical interconnection schemes involving the flip-chip integration of submicron CMOS ICs with GaAs chips containing 2-D arrays of multiple quantum well diode optical receivers an transmitters.
A three-dimensional multi-stage optical interconnection network is proposed for massivelyparallel processors. The interconnection network employs beamsteering vertical cavity surface-emitting lasers (VCSEL) as space-...
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ISBN:
(纸本)0818675918
A three-dimensional multi-stage optical interconnection network is proposed for massivelyparallel processors. The interconnection network employs beamsteering vertical cavity surface-emitting lasers (VCSEL) as space-division switching elements, and micromachined micro-Fresnel lenses as free-space optical elements. The entire switching network is integrated on a Si chip using the free-space micro-optical bench technology (FSMOB). All the optics in the switching network has been pre-aligned during the design process. The laser arrays and detector arrays are monolithically fabricated on the same smart pixel plane. Two smart pixel planes are mounted face-to-face and optically connected by the Fresnel lens arrays between them. The number of switching stages can be increased by vertically cascading switching arrays, forming a three- dimensional interconnect network This configuration greatly reduces the physical dimensions of the system, and can be readily scaled up to large switching networks. We have successfully implemented an 8x8 banyan network by cascading two folded cavity.
We propose a novel planar optical interconnection scheme for 100 Gb/s optical packet address detection, which consists of waveguide grating couplers and a diffractive microlens integrated on a glass substrate 3-dimens...
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We propose a novel planar optical interconnection scheme for 100 Gb/s optical packet address detection, which consists of waveguide grating couplers and a diffractive microlens integrated on a glass substrate 3-dimensionally. Length and duty cycle of the grating couplers have been determined on the bases of the ray-optic propagation-mode analysis in a slab waveguide and of the rigorous coupled-wave diffraction analysis for out-coupled radiation-modes. The 3-dimensionally integrated planar optics makes it possible to connect each address bit-signals of TEo-waveguide mode to the detector with a power uniformity of 6.4% and a total coupling efficiency of 72.3%.
We describe a flexible all-optical interconnect scheme for massivelyparallelprocessing, capable of providing 250 channels and an information capacity of 250 Gb/s. using available and/or demonstrated technologies, we...
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We describe a flexible all-optical interconnect scheme for massivelyparallelprocessing, capable of providing 250 channels and an information capacity of 250 Gb/s. using available and/or demonstrated technologies, we can build fully tunable transmitter arrays and receivers. These essentially act to create a randomly accessible 250×250 crossbar switch, connecting up to 500 processors in a single-level system. The multiplexing and de-multiplexing can be done with sufficient speed to satisfy requirements for massive parallelprocessing. The crossbar switch can provide 250,000 1-Mb packet connections per second. A multi-level system can provide thousands to millions of simultaneous connections, at the cost of greater control complexity. A reservation scheme for the control of the one- and two-level switch is illustrated and computer simulation of the scheme demonstrated. We also propose a `pilot' token scheme for the multi-channel Express Bus (E-bus) on which packet switching can be performed. We believe that recent advancements have made the system technically feasible, and (with OEIC integration) practical and cost effective. Other related interconnect/network issues are discussed.
A neural network architecture is described which uses stochastic processing techniques to perform the weighted-input multiplication, summation and thresholding processes of a neuron using the optimal amount of hardwar...
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A neural network architecture is described which uses stochastic processing techniques to perform the weighted-input multiplication, summation and thresholding processes of a neuron using the optimal amount of hardware. It will be argued that the advantage of this approach is that it will allow large neural networks to be fabricated with relatively small amounts of hardware. The architecture allows a choice to be made between the speed and accuracy of processing, as well as a choice of hardware. Implementations of a bit stream neuron using electronic, optoelectronic and optical hardware are developed and their capabilities are compared based on speed of processing and network size. The aim of this study is to investigate the capabilities of optical logic in distributed processing systems, together with the use of the optical thyristor as logic elements. It is shown that opticalprocessing and optical interconnection allows a simplification of the processing sequence and allows the parallelism of distributed systems to be utilized.
The optical interconnection plays an important role of realization in massivelyparallel computation. This is well recognized, but it is not clear how the optical interconnection works in parallelprocessing. In this ...
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The optical Transpose Interconnection System (OTIS) proposed in [13] makes use of free-space optical interconnects to augment an electronic system with non-local interconnections. In this paper we show how these conne...
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ISBN:
(纸本)0818675918
The optical Transpose Interconnection System (OTIS) proposed in [13] makes use of free-space optical interconnects to augment an electronic system with non-local interconnections. In this paper we show how these connections can be used to implement a large-scale system with a given network topology using small copies of a similar topology. In particular we show that, using OTIS, an N-2 node 4-D mesh can be constructed from N copies of the N-node 2-D mesh, an N-2 node hypercube can be constructed from N copies of the N-node hypercube, and an (N-2, alpha(2), c/2) expander can be constructed from N copies of an (N, alpha, c) expanders, all with small slowdown. We also show how this expander construction can be used to build multibutterfly networks in a scalable fashion. Finally, we demonstrate how the OTIS connections can be used to produce a bit-parallel crossbar using many copies of bit-serial crossbars with minimal overhead.
This paper demonstrates that the potential for very high speed computation provided by optical technology can be achieved for important computational problems including the fast Fourier transform and sorting. First a ...
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ISBN:
(纸本)0818675918
This paper demonstrates that the potential for very high speed computation provided by optical technology can be achieved for important computational problems including the fast Fourier transform and sorting. First a programming model that captures the 'time-of-flight' characteristics of optical fibers and switching elements is presented. Then it is shown that the FFT and the radix sort algorithms can both be reduced to the computational kernel of 'packing' intermediate data results that are continuously moving through an optical fiber. New algorithms are developed for the general packing problem, and the details of how to implement them in optics are presented. The resulting systems have the potential for operating at clock rates that are two or more orders of magnitude higher than conventional computers.
An ultra-dense optical interconnection network is proposed for massivelyparallel processors. using two-dimensional arrays of beam-steering vertical cavity surface-emitting lasers (VCSEL) as space-division switching e...
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An ultra-dense optical interconnection network is proposed for massivelyparallel processors. using two-dimensional arrays of beam-steering vertical cavity surface-emitting lasers (VCSEL) as space-division switching elements, a single-chip, free-space photonic banyan network (or other multi-stage networks) can be constructed. Our scheme does not require critical optical alignment and can be easily packaged in compact chips. The optical beam steering of VCSELs are realized with an integrated beam router. Steering angles as large as 10° from surface-normal direction has been demonstrated. The VCSEL has a threshold current of 4 mA and output power of 1 mW (for 4 μm×8 μm device) and a modulation bandwidth of 10 GHz. Dynamic switching of optical beam angles at 2 GHz has been demonstrated.
4 channel multiplexing for 64 bit two dimensional (2-D) paralleloptical data link based upon optical space-CDMA is experimentally demonstrated by using newly developed modules of optical spatial encoder and decoder. ...
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4 channel multiplexing for 64 bit two dimensional (2-D) paralleloptical data link based upon optical space-CDMA is experimentally demonstrated by using newly developed modules of optical spatial encoder and decoder. Each 8×8 bit-plane (64 bit parallel data) is optically encoded with an 8×8 2-D optical orthogonal signature pattern. The encoded bit-planes are spatially multiplexed, and it is transmitted through an image fiber having 105 cores. Each receiver can recover the intended input bit-plane via the optical decoding process. Total error-rate is 2.73%. This result will encourage the application of optical space-CDMA to future high-throughput 2-D parallel data links connecting massivelyparallel processors.
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