Several fine and medium grain parallel computer architectures comprise multiple stages of 2-D processing element arrays. The parallel massive interconnections between two such stages can be implemented in optics. Stra...
详细信息
parallel optoelectronic multiplexers benefit from the large number of I/O channels available in free-space optics. The comparative advantage of parallel over serial I/O is less power dissipation per unit area and less...
详细信息
Opto-electronic reconfigurable interconnection networks are limited by significant control latency when used in large multiprocessor systems. This latency is the time required to analyze the current traffic and reconf...
详细信息
Opto-electronic reconfigurable interconnection networks are limited by significant control latency when used in large multiprocessor systems. This latency is the time required to analyze the current traffic and reconfigure the network to establish the required paths. The goal of latency hiding is to minimize the effect of this control overhead. In this paper, we introduce a technique that performs latency hiding by learning the patterns of communication traffic and using that information to anticipate the need for communication paths. Hence, the network provides the required communication paths before a request for a path is made. In this study, the communication patterns (memory accesses) of a parallel program are used as input to a time delay neural network (TDNN) to perform on-line training and prediction. These predicted communication patterns are used by the interconnection network controller that provides routes for the memory requests. Based on our experiments, the neural network was able to learn highly repetitive communication patterns, and was thus able to predict the allocation of communication paths, resulting in a reduction of communication latency.
An important issue in the design of interconnection networks for massivelyparallel computers is scalability. Size-scalability refers to the property that the number of nodes in the network can be increased with negli...
详细信息
The Melbourne University Optoelectronic Multicomputer Project is investigating dense optical interconnection networks capable of providing lowlatency data transfer of 32 or 64 bits. The networks we have developed do n...
详细信息
We present the design of a wavelength division multiplexed fiber optic bus for multiprocessors that allows both the shared memory model and the distributed memory model to be supported efficiently. We establish this b...
详细信息
We present AMOEBA: a single-chip asynchronous multiprocessor optoelectronic bit-sliced arrayed crossbar switch intended to provide switched interconnection between multiple processors in a distributed computing enviro...
详细信息
We present AMOEBA: a single-chip asynchronous multiprocessor optoelectronic bit-sliced arrayed crossbar switch intended to provide switched interconnection between multiple processors in a distributed computing environment. AMOEBA relies on optoelectronic-VLSI integration, free-space optical interconnects, and wavelength-and-space-division multiplexed networking on single-mode fiber. We report the implementation and testing of a first generation, 16-channel prototype of the switch and a compact opto-mechanical transceiver package that accomplishes the free-space-to-fiber interfacing.
We describe a fully configurable, parallel architecture based on free-space optical communication. The noninterference and free-space transmission of light are exploited to provide parallel and arbitrary communication...
详细信息
Systolic arrays have traditionally provided efficient, high performance execution for computation intensive applications. Despite the extensive research in systolic arrays, system designers must continually incorporat...
详细信息
Systolic arrays have traditionally provided efficient, high performance execution for computation intensive applications. Despite the extensive research in systolic arrays, system designers must continually incorporate new technological advances to improve node communications, I/O bandwidth, and programmability. This paper presents optoelectronic interconnect as a communication method for systolic arrays in early image processing applications. Optoelectronic interconnects provide potentially high I/O bandwidth required to maintain high utilization rate for systolic arrays. In addition, optoelectronic interconnects provides a two-dimensional focal-plane topology ideal for systolic image processing systems. This paper introduces two new systolic architectures that incorporate integrated optoelectronics to provide an extremely compact, high performance, highly efficient image processing system. Several important early image processing applications developed for these architectures are also described.
To successfully exploit the benefits of optical technology in a tightly-coupled multicomputer, the architectural design must reflect both the advantages of optics and the limitations of optics. This paper describes a ...
暂无评论