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Fine-Grained parallel Traversals of Irregular Data Structures 12

Fine-Grained Parallel Traversals of Irregular Data Structure...

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21st international conference on parallel architectures and compilation techniques (PACT)

作者： Ren, Bin Agrawal, Gagan Larus, James R. Mytkowicz, Todd Poutanen, Tomi Schulte, Wolfram Ohio State Univ Dept Comp Sci & Engn Columbus OH 43210 USA Microsoft Res Redmond WA 98052 USA

ISBN: (纸本)9781450311823

Fine-grain data parallelism is increasingly common in mainstream processors in the form of long vectors and on-chip GPUs. This paper develops compiler and runtime support to exploit such data parallelism for non-numeric, non-graphic, irregular parallel tasks that perform simple computations while traversing many independent, irregular data structures, like trees and graphs. We vectorize the traversal of trees and graphs by treating a set of irregular data structures as a parallel control-flow graph and compiling the traversal into a domain-specific bytecodes. We produce a SIMD interpreter for these bytecodes, so each lane of a SIMD unit traverses one irregular data structure. Despite the overhead of interpretation, we demonstrate significant increases in single-core performance over optimized baselines.

关键词： Irregular Data Structure Fine Grained parallelism SIMD

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MaSiF: Machine Learning Guided Auto-tuning of parallel Skeletons 12

MaSiF: Machine Learning Guided Auto-tuning of Parallel Skele...

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21st international conference on parallel architectures and compilation techniques (PACT)

作者： Collins, Alexander Fensch, Christian Leather, Hugh Univ Edinburgh Sch Informat Edinburgh Midlothian Scotland

ISBN: (纸本)9781450311823

We present MaSiF, a novel tool to auto-tune parallelization parameters of skeleton parallel programs. It reduces the cost of searching the optimization space using a combination of machine learning and linear dimensionality reduction. To auto-tune a new program, a set of program features is determined statically and used to compute k nearest neighbors from a set of training programs. Previously collected performance data for the nearest neighbors is used to reduce the size of the search space using Principal Components Analysis. This results in a set of eigenvectors that are used to search the reduced space. MaSiF achieves 88% of the performance of the oracle, which searches a random set of 10,000 parameter values. MaSiF searches just 45 points, or 0.45% of the optimization space, to achieve this performance. MaSiF provides an average speedup of 1.18x over parallelization parameters chosen by a human expert.

关键词： Auto-tuning FastFlow Machine Learning Multi-core parallel Skeletons

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Polyhedral-Model Guided Loop-Nest Auto-Vectorization 09

Polyhedral-Model Guided Loop-Nest Auto-Vectorization

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18th international conference on parallel architectures and compilation techniques

作者： Trifunovic, Konrad Nuzman, Dorit Cohen, Albert Zaks, Ayal Rosen, Ira INRIA Saclay Saclay France IBM Corp Haifa Res Lab Haifa Israel

ISBN: (纸本)9780769537719

Optimizing compilers apply numerous interdependent optimizations, leading to the notoriously difficult phase-ordering problem - that of deciding which transformations to apply, and in which order. Fortunately, new infrastructures such as the polyhedral compilation framework host a variety of transformations, facilitating the efficient exploration and configuration of multiple transformation sequences. Many powerful optimizations, however, remain external to the polyhedral framework, including vectorization. The low-level, target-specific aspects of vectorization for fine-grain SIMD has so far excluded it from being part of the polyhedral framework. In this paper we examine the interactions between loop transformations of the polyhedral framework and subsequent vectorization. We model the performance impact of the different loop transformations and vectorization strategies, and then show how this cost model can be integrated seamlessly into the polyhedral representation. This predictive modelling facilitates efficient exploration and educated decision making to best apply various polyhedral loop transformations while considering the subsequent effects of different vectorization schemes. Our work demonstrates the feasibility and benefit of tuning the polyhedral model in the context of vectorization. Experimental results confirm that our model has accurate predictions, providing speedups of over 2.0x on average over traditional innermost-loop vectorization on PowerPC970 and Cell-SPU SIMD platforms.

关键词： parallel processing Predictive models Production Cost function parallel architectures Bridges Optimizing compilers Decision making Context modeling Concurrent computing

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Concurrent Predicates: A Debugging Technique for Every parallel Programmer

Concurrent Predicates: A Debugging Technique for Every Paral...

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22nd international conference on parallel architectures and compilation techniques (PACT)

作者： Gottschlich, Justin Pokam, Gilles Pereira, Cristiano Wu, Youfeng Intel Corp Santa Clara CA 95051 USA

ISBN: (纸本)9781479910212

To reduce the complexity of debugging multithreaded programs, researchers have developed many techniques that automatically detect bugs that arise from shared memory errors. These techniques can identify a wide range of bugs, but it can be challenging for a programmer to reproduce a specific bug that he or she is interested in using such techniques. This is because these techniques were not intended for individual bug reproduction but rather an exploratory search for possible bugs. To address this concern we present concurrent predicates (CPs) and concurrent predicate expressions (CPEs), which allow programmers to single out a specific bug by specifying the schedule and program state that must be satisfied for the bug to be reproduced. We present the recipes, that is, the mechanical processes, we use to reproduce data races, atomicity violations, and deadlocks with CP and CPE. We then show how these recipes apply to the diagnosis and reproduction of bugs from 13 hand-crafted bugs, five real-world application bugs from RADBench, and three previously unresolved bugs from ***, which now includes the fixes we generated using CP and CPE.

关键词： algorithms reliability verification

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Revisiting Sorting for GPGPU Stream architectures 10

Revisiting Sorting for GPGPU Stream Architectures

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19th international conference on parallel architectures and compilation techniques

作者： Merrill, Duane G. Grimshaw, Andrew S. Univ Virginia Dept Comp Sci Charlottesville VA 22903 USA

ISBN: (纸本)9781450301787

This poster presents efficient strategies for sorting large sequences of fixed-length keys (and values) using GPGPU stream processors. Compared to the state-of-the-art, our radix sorting methods exhibit speedup of at least 2x for all generations of NVIDIA GPGPUs, and up to 3.7x for current GT200-based models. Our implementations demonstrate sorting rates of 482 million key-value pairs per second, and 550 million keys per second (32-bit). For this domain of sorting problems, we believe our sorting primitive to be the fastest available for any fully-programmable microarchitecture. These results motivate a different breed of parallel primitives for GPGPU stream architectures that can better exploit the memory and computational resources while maintaining the flexibility of a reusable component. Our sorting performance is derived from a parallel scan stream primitive that has been generalized in two ways: (1) with local interfaces for producer/consumer operations (visiting logic), and (2) with interfaces for performing multiple related, concurrent prefix scans (multi-scan).

关键词： GPU sorting radix sorting prefix scan kernel fusion

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XStream: Cross-core Spatial Streaming based MLC Prefetchers for parallel Applications in CMPs 14

XStream: Cross-core Spatial Streaming based MLC Prefetchers ...

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23rd international conference on parallel architectures and compilation techniques (PACT)

作者： Panda, Biswabandan Balachandran, Shankar Indian Inst Technol Madras Dept Comp Sci & Engn Madras Tamil Nadu India

ISBN: (纸本)9781450328098

Hardware prefetchers are commonly used to hide and tolerate off-chip memory latency. Prefetching techniques in the literature are designed for multiple independent sequential applications running on a multicore system. In contrast to multiple independent applications, a single parallel application running on a multicore system exhibits different behavior. In case of a parallel application, cores share and communicate data and code among themselves, and there is commonality in the demand miss streams across multiple cores. This gives an opportunity to predict the demand miss streams and communicate the predicted streams from one core to another, which we refer as cross-core stream communication. We propose cross-core spatial streaming (XStream), a practical and storage-efficient cross-core prefetching technique. XStream detects and predicts the cross-core spatial streams at the private mid level caches (MLCs) and sends the predicted streams in advance to MLC prefetchers of the predicted cores. We compare the effectiveness of XStream with the ideal cross-core spatial streamer. Experimental results demonstrate that, on an average (geomean), compared to the state-of-the-art spatial memory streaming, storage efficient XStream reduces the execution time by 11.3% (as high as 24%) and 9% (as high as 29.09%) for 4-core and 8-core systems respectively.

关键词： Prefetching multi-core

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Evaluating the Cost of Atomic Operations on Modern architectures 24

Evaluating the Cost of Atomic Operations on Modern Architect...

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24th international conference on parallel Architecture and compilation (PACT)

作者： Schweizer, Hermann Besta, Maciej Hoefler, Torsten ETH Dept Comp Sci Zurich Switzerland

ISBN: (纸本)9781467395243

Atomic operations (atomics) such as Compare-andSwap (CAS) or Fetch-and-Add (FAA) are ubiquitous in parallel programming. Yet, performance tradeoffs between these operations and various characteristics of such systems, such as the structure of caches, are unclear and have not been thoroughly analyzed. In this paper we establish an evaluation methodology, develop a performance model, and present a set of detailed benchmarks for latency and bandwidth of different atomics. We consider various state-of-the-art x86 architectures: Intel Haswell, Xeon Phi, Ivy Bridge, and AMD Bulldozer. The results unveil surprising performance relationships between the considered atomics and architectural properties such as the coherence state of the accessed cache lines. One key finding is that all the tested atomics have comparable latency and bandwidth even if they are characterized by different consensus numbers. Another insight is that the design of atomics prevents any instructionlevel parallelism even if there are no dependencies between the issued operations. Finally, we discuss solutions to the discovered performance issues in the analyzed architectures. Our analysis can be used for making better design and algorithmic decisions in parallel programming on various architectures deployed in both off-the-shelf machines and large compute systems.

关键词： Atomic Operations CPU architecture parallel programming Read-modify-write

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Automatic Algorithm-Based Fault Tolerance (AABFT) of Stencil Computations 32

Automatic Algorithm-Based Fault Tolerance (AABFT) of Stencil...

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32nd international conference on parallel architectures and compilation techniques (PACT)

作者： Narmour, Louis Derrien, Steven Rajopadhye, Sanjay Univ Rennes Inria CNRS IRISA Rennes France Colorado State Univ Ft Collins CO 80523 USA

ISBN: (纸本)9798350342543

In this work, we study fault tolerance of transient errors, such as those occurring due to cosmic radiation or hardware component aging and degradation, using Algorithm-Based Fault Tolerance (ABFT). ABFT methods typically work by adding some additional computation in the form of invariant checksums which, by definition, should not change as the program executes. By computing and monitoring checksums, it is possible to detect errors by observing differences in the checksum values. However, this is challenging for two key reasons: (1) it requires careful manual analysis of the input program, and (2) care must be taken to subsequently carry out the checksum computations efficiently enough for it to be worth it. Prior work has shown how to apply ABFT schemes with low overhead for a variety of input programs. Here, we focus on a subclass of programs called stencil applications, an important class of computations found widely in various scientific computing domains. We propose a new compilation scheme to automatically analyze and generate the checksum computations. To the best of our knowledge, this is the first work to do such a thing in a compiler. We show that low overhead code can be easily generated and provide a preliminary evaluation of the tradeoff between performance and effectiveness.

关键词： fault-tolerance program transformations polyhedral compilation stencils

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Interprocedural Load Elimination for Dynamic Optimization of parallel Programs 09

Interprocedural Load Elimination for Dynamic Optimization of...

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18th international conference on parallel architectures and compilation techniques

作者： Barik, Rajkishore Sarkar, Vivek Rice Univ Dept Comp Sci Houston TX 77251 USA

ISBN: (纸本)9780769537719

Load elimination is a classical compiler transformation that is increasing in importance for multi-core and many-core architectures. The effect of the transformation is to replace a memory access, such as a read of an object field or an array element, by a read of a compiler-generated temporary that can be allocated in faster and more energy-efficient storage structures such as registers and local memories (scratchpads). Unfortunately, current just-in-time and dynamic compilers perform load elimination only in limited situations. In particular, they usually make worst-case assumptions about potential side effects arising from parallel constructs and method calls. These two constraints interact with each other since parallel constructs are usually translated to low-level runtime library calls. In this paper, we introduce an interprocedural load elimination algorithm suitable for use in dynamic optimization of parallel programs. The main contributions of the paper include: a) an algorithm for load elimination in the presence of three core parallel constructs - async, finish, and isolated, b) efficient side-effect analysis for method calls, c) extended side-effect analysis for parallel constructs using an Isolation Consistency memory model, and d) performance results to study the impact of load elimination on a set of standard benchmarks using an implementation of the algorithm in Jikes RVM for optimizing programs written in a subset of the X10 v1.5 language. Our performance results show decreases in dynamic counts for getfield operations of up to 99.99%, and performance improvements of up to 1.76x on 1 core, and 1.39x on 16 cores, when comparing the algorithm in this paper with the load elimination algorithm available in Jikes RVM.

关键词： Load elimination scalar replacement parallel program dynamic compilation dynamic optimization memory model

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Efficient personalized communication on wormhole networks

Efficient personalized communication on wormhole networks

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1997 international conference on parallel architectures and compilation techniques

作者： Petrini, F Vanneschi, M Int Computer Science Inst Berkeley United States

ISBN: (纸本)0818680903

Bridging models, as the BSP, tend to abstract the characteristics of the interconnection networks using a small set of parameters, by dividing the computation in supersteps and organizing the communication in global patterns called h-relations. In this paper we evaluate, through experimental results conducted on a wormhole-routed by-dimensional torus and a quaternary fat-tree with 256 processing nodes, the execution time of three families of h-relations with variable degree of imbalance. We also prove a strong result that links the communication performance of the fat-tree with the BSP abstraction of the the interconnection network. Given a generic h-relation, we can provide a value of g that, in the worst case, slightly over-estimates the completion time and is very close to optimality.

关键词： performance evaluation parallel architectures and computation models h-relations BSP interconnection networks k-ary n-cubes k-ary n-trees

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