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Leveraging Neural Networks to Enhance Large-Scale Data processing Performance

Leveraging Neural Networks to Enhance Large-Scale Data Proce...

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Smart Generation Computing, Communication and Networking (SMART GENCON), international conference on

作者： Megha Pandey Vinay Kumar S B Jatin Khurana B. Kalpana Kishor R. Pathak Mukesh Kumar Maharishi School of Engineering and Technology Maharishi University of Information Technology Uttar Pradesh India −1 Electronics and Communication Engineering Faculty of Engineering and Technology JAIN (Deemed-to-be University) Bangalore Karnataka India Centre of Interdisciplinary Research in Business and Technology Chitkara University Institute of Engineering and Technology Chitkara University Punjab India Department of Science and Humanities Prince Shri Venkateshwara Padmavathy Engineering College Chennai Department of Information Technology Vishwakarma Institute of Information Technology Pune India Department of Mechanical Engineering Vivekananda Global University Jaipur India

Recent advances in neural networks have enabled them to become powerful tools in data processing for tasks such as pattern recognition and classification. This has enabled neural networks to be applied to large-scale data processing problems, where they have been shown to perform very well. However, due to the large amount of data involved in such tasks, it is essential that the processing performance is also improved. This paper presents several methods to leverage available resources such as distributed computing and improved algorithmic techniques to improve the performance of large-scale data processing tasks using neural networks. Examples of such techniques are given for both supervised and unsupervised learning tasks, which can significantly enhance the performance of large-scale data processing applications. The results of several experiments are presented, demonstrating the effectiveness of the proposed techniques. The authors also provide insights for future work that could further enhance the capabilities of neural networks when applied to large-scale data processing applications.

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Highly Scalable parallel Checksums 27

Highly Scalable Parallel Checksums

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27th IEEE international conference on parallel and distributed Systems, ICPADS 2021

作者： Siebert, Christian Heinrich Heine University Düsseldorf Centre for Information and Media Technology Düsseldorf Germany

ISBN: (纸本)9781665408783

Checksums are used to detect errors that might occur while storing or communicating data. Checking the integrity of data is well-established, but only for smaller data sets. Contrary, supercomputers have to deal with huge amounts of data, which introduces failures that may remain undetected. Therefore, additional protection becomes a necessity at large scale. However, checking the integrity of larger data sets, especially in case of distributed data, clearly requires parallel approaches. We show how popular checksums, such as CRC-32 or Adler-32, can be parallelized efficiently. This also disproves a widespread belief that parallelizing aforementioned checksums, especially in a scalable way, is not possible. The mathematical properties behind these checksums enable a method to combine partial checksums such that its result corresponds to the checksum of the concatenated partial data. Our parallel checksum algorithm utilizes this combination idea in a scalable hierarchical reduction scheme to combine the partial checksums from an arbitrary number of processing elements. Although this reduction scheme can be implemented manually using most parallel programming interfaces, we use the Message Passing Interface, which supports such a functionality directly via non-commutative user-defined reduction operations. In conjunction with the efficient checksum capabilities of the zlib library, our algorithm can not only be implemented conveniently and in a portable way, but also very efficiently. Additional shared-memory parallelization within compute nodes completes our hybrid parallel checksum solutions, which show a high scalability of up to 524,288 threads. At this scale, computing the checksums of 240 TiB data took only 3.4 seconds for CRC-32 and 2.6 seconds for Adler-32. Finally, we discuss the APES application as a representative of dynamic supercomputer applications. Thanks to our scalable checksum algorithm, even such applications are now able to detect many errors withi

关键词： Supercomputers

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A High-Speed Multiplier Design Using 2—Bit Reordering 4:3 Counter in a Wallace Tree Structure

A High-Speed Multiplier Design Using 2—Bit Reordering 4:3 C...

引用

international conference on Trends in Electronics and Informatics (ICEI)

作者： Saleem Syed Abdul Khader Khaderabad Sahithi Ankirapalli Swathi Lingamgunta Sasi Priyanka Thammisetty Jaffar Ali Syed Dept. of Electronics and Communication Engineering Annamacharya Institute of Technology and Sciences Kadapa India

ISBN: (数字)9798331544607

ISBN: (纸本)9798331544614

It is known that the multiplier is widely applied, and to produce the outputs for the next stage, there is a reliance on the previous stage. Due to this, the multiplication process takes time to complete. As the binary bit counts of the multiplier and multiplicand increase, it takes longer to generate the output. This longer delay can severely impair the overall performance of digital systems, especially in applications requiring high-speed computations. Therefore, optimizing the Multiplier for both speed and power efficiency is crucial to enhancing the performance of modern computing architectures. To achieve this optimization, various techniques such as parallel processing and reduced gate counts can be employed. Moreover, utilising advanced algorithms and hardware accelerators can enhance the efficiency of these multipliers in challenging computational settings. This will affect the circuit performance. A new technique known as the reordering technique is implemented in this project to enhance the multiplier in terms of speed and efficiency. This method is implemented by separating the high-state bits from the low-state bits using the reordering circuit, and then the separated bits are processed in the usual manner. This helps in the reduction of critical path latency, which benefits by enhancing the circuit's power consumption as less power is being released as heat or another form.

关键词： Micromechanical devices Power demand Logic gates parallel processing Market research Delays Table lookup Informatics Adders Optimization

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Privacy-Preserving Federated Learning through Clustered Sampling on Fine-Tuning distributed non-iid Large Language Models

Privacy-Preserving Federated Learning through Clustered Samp...

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IEEE international conference on Big Data and Cloud Computing (BdCloud)

作者： Sheng Yun Zakirul Alam Bhuiyan Md. Taufiq Al Hasib Sadi Shen Su Department of Computer and Information Sciences Fordham University New York USA Department of Electrical & Computer Engineering North South University Dhaka Bangladesh Cyberspace Institute of Advanced Technology Guangzhou University Guangzhou China

Recently, Large Language Models (LLMs) have been a phenomenal trend in the Artificial intelligence field. However, training and fine-tuning can be challenging because of privacy concerns and limited computing resources. Federated Learning (FL) has emerged as a novel machine learning framework offering privacy protection. The challenges in applying FL to real-world applications include dealing with heterogeneous data, poor client updates, and client selection. This paper introduces Privacy-preserving Federated Learning through Clustered Sampling on LLMs (FCLM), a framework that clusters models by their distribution similarity. It helps the model group similar models to improve text data heterogeneity handling and privacy concerns in distributed machine-learning environments. The FCLM framework is implemented and evaluated using popular Language models and text data. The framework shows a robust performance over the heterogeneous text data, which can further extend to the use of more complex LLMs.

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Arabic sign Language Recognition: Towards a Dual Way Communication System Between Deaf and Non-Deaf People 22

Arabic sign Language Recognition: Towards a Dual Way Communi...

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22nd IEEE/ACIS international conference on Software Engineering, Artificial Intelligence, Networking and parallel/distributed Computing (SNPD-Fall)

作者： Ben Hamouda, Souha Gabsi, Wafa Univ Sfax ReDCAD Lab Natl Sch Engineers Sfax BP 1173 Sfax 3038 Tunisia Fac Sci Gabes City Riadh Zerig 6029 Gabes Tunisia

ISBN: (纸本)9781665404037

One key perspective when communicating with deaf people is sign language recognition. Many experts agree upon the fact that using a system communication is a key for bridging the gap between deaf and non deaf people since ordinary people can not exchange using the sign language. As a result, researchers, deaf people, parents and deaf-mute community are striving to have a bidirectional communication system based on translation with lower costs. The importance of the research is related to its goal of helping these categories of unvoiced people communicate with others and enhance their contributions to growth and capacity building and vice versa. This paper gives an overview of the most used techniques and technologies (gloves, android application, image processing, ...) in order to translate sign language to written or spoken language. Furthermore, this paper provides a critical and comparative analysis of the studied approaches and stands out major challenges to overcome their limits. Finally, we propose in this paper a dual way communication system ensuring arabic sign language translation into spoken language based on image processing and deep learning.

关键词： Arabic sign language Gesture recognition Image processing Machine learning mobile application dual communication system

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Exploring Quantum Processors in Decentralized Edge Computing for Improved Data processing

Exploring Quantum Processors in Decentralized Edge Computing...

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Machine Learning and Autonomous Systems (ICMLAS), international conference on

作者： Harshad Pitkar Luddy School of Informatics Computing and Engineering Indiana University Bloomington IN USA

ISBN: (数字)9798331505745

ISBN: (纸本)9798331505752

The rapid growth of data generated by Internet of Things (IoT) devices necessitates the development of advanced computational frameworks that can efficiently handle real-time data processing. Traditional cloud and edge computing systems, while effective, face significant challenges, including high latency, limited computational resources, and data transfer bottlenecks. To address these issues, this study introduces a hybrid approach that integrates quantum computing into the edge-cloud continuum. The proposed method utilizes Quantum- Neural Networks (QNNs) in conjunction with local edge processing, leveraging quantum autoencoders for feature compression, and incorporating fully decentralized edge computing with quantum processors to enhance data processing capabilities. Additionally, a hybrid model combining QNNs with classical machine learning techniques is implemented at the edge for improved classification accuracy. The proposed system's performance is evaluated through extensive experiments across multiple datasets, comparing the results of quantum-based models with traditional classical and hybrid approaches. The results show a significant improvement in classification accuracy, reduced feature compression time, and enhanced processing efficiency, particularly in resource-constrained environments. The results underscore the potential of quantum machine learning in real-time, large-scale applications, marking an important step toward the practical integration of quantum computing in distributed computing systems.

关键词： Quantum computing Accuracy Program processors Computational modeling Autoencoders Machine learning Real-time systems Computational efficiency Internet of Things Edge computing

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Optimal Design Method for Uniform MagneticField of Two parallel Coils Using Numerical Cloud Images and Machine Learning

Optimal Design Method for Uniform MagneticField of Two Paral...

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international conference on High Voltage Engineering and Application, ICHVE

作者： Zipeng Cheng Qizheng Ye Cheng Ye Li Wenhua Wu School of Electrical and Electronic Engineering Huazhong University of Science and Technology Wuhan China

ISBN: (数字)9798350374988

ISBN: (纸本)9798350374995

In high-voltage devices, the demand for the uniform magnetic fields is very high. The existing methods still have shortcomings in terms of optimizing region, complexity, and universality. Herein, we propose a method for designing uniform magnetic fields based on numerical cloud images and machine learning. First, the magnetic-field distribution of the two parallel coils determined using two shape parameters is calculated using finite element software and is drawn. Thereafter, a dataset of 400 cloud images is created with different magnetic induction intensity distributions using different coil-shape parameters. Next, we employ image-processing techniques to extract nine statistical features from the gray-level information in the images. Models are trained through machine learning to predict electrode-shape parameters based on the gray-level image features. Finally, the magnetic-field image of the expected ideal uniform field is artificially set. In addition, the coil-shape parameters from which the uniform magnetic-field is produced are predicted by the models. The optimized design of the two parallel coils improves the magnetic-field uniformity in the axial and radial center regions compared to the Helmholtz coils. The proposed method provides an accurate and new solution for optimizing the design of a uniform magnetic-field.

关键词： Coils Magnetic resonance imaging Design methodology Machine learning High-voltage techniques Predictive models Feature extraction

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PRACO: A Photonic Residue-Number Architecture for Collective Operations

PRACO: A Photonic Residue-Number Architecture for Collective...

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IEEE international conference on Rebooting Computing (ICRC)

作者： Jiaxin Peng Xiaoxuan Ma Tarek El-Ghazawi Department of Electrical and Computer Engineering The George Washington University Washington D.C. USA

ISBN: (数字)9798331541279

ISBN: (纸本)9798331541286

Collective operations that involve multiple or all processes/threads within a parallel program are critical in multicore chips and parallel systems, particularly for data-intensive applications. However, many existing electrical network systems struggle to efficiently support these operations, leading to significant overhead and reduced performance. Optical solutions have been proposed to address the challenges due to their high-speed transmission and low-power consumption. Moreover, the synergy between photonic technologies and Residue Number System offers an efficient alternative for computing because of their high parallelism and the opportunity for compute-in-network ***, we propose PRACO, a Photonic Residue-Number Architecture for Collective Operations. It establishes a photonic network at the chip level to accelerate communication, computation, and synchronization among multi-cores in the system. Moreover, its compute-in-network capability allows for performing computations during data transmission, which minimizes data movement and further reduces latency and power consumption. Furthermore, the network enables high-speed synchronization barriers, which allows faster coordination between cores, improving overall system efficiency. Compared to an electrical network, our simulation results show that PRACO achieves up to an order of magnitude speedup for collective operations, along with a significant decrease in energy consumption.

关键词： Power demand Multicore processing Simulation Computer architecture parallel processing Optical fiber communication Synchronization Optical devices Photonics High-speed optical techniques

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PK-GRAPH: Partitioned k²-Trees to Enable Compact and Dynamic Graphs in Spark GraphX 28th

PK-GRAPH: Partitioned k<SUP>2</SUP>-Trees to Enable Compact ...

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28th international conference on Cooperative Information Systems (CoopIS)

作者： Morais, Bruno Coimbra, Miguel E. Veiga, Luis Univ Lisbon INESC ID IST R Alves Redol 9 Lisbon Portugal

ISBN: (纸本)9783031178344;9783031178337

Graphs are becoming increasingly larger, with datasets having millions of vertices and billions (or even trillions) of edges. As a result, the ability to fit the entire graph into the main memory of a single machine faces challenges in common hardware, even more so in edge/IoT-like devices (i.e., more energy efficient but also more resource constrained). Reading the graph from secondary storage may pose in itself significant overhead, negatively impacting query performance and storage requirements. It thus becomes relevant to explore techniques to optimize the storage of graphs, specially in memory, in a way that circumvents space limitations, while avoiding compromising the performance of processing. We observe that current graph storage systems manage the graph representation by storing graphs in an uncompressed format, either: i) in a shared architecture which leads to a higher space overhead and the inability to represent the graph entirely in main memory, or ii) in a distributed architecture, where the graph dataset is partitioned over a cluster of machines with each one storing in main memory only a fragment (shard) of the (uncompressed) graph. We present PK-GRAPH, our proposal which extends a distributed graph processing system, highly used in academia and industry (Spark GraphX), in order to deploy the use of a compressed graph representation, with added support for dynamic updatable graphs (not currently supported in GraphX). Our experimental results show that PK-GRAPH can achieve up to 50% lower graph memory usage, while maintaining competitive performance in executing typical graph operations used in common applications.

关键词： Graph representation Graph databases Graph processing systems Optimization Compression

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Scaling a Hippocampus Model with GPU parallelisation and Test-Driven Refactoring 1

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11th international conference on Biomimetic and Biohybrid Systems (Living Machines)

作者： Stevenson, Jack Fox, Charles Univ Lincoln Sch Comp Sci Lincoln England

ISBN: (数字)9783031204708

ISBN: (纸本)9783031204692;9783031204708

The hippocampus is the brain area used for localisation, mapping and episodic memory. Humans and animals can outperform robotic systems in these tasks, so functional models of hippocampus may be useful to improve robotic navigation, such as for self-driving cars. Previous work developed a biologically plausible model of hippocampus based on Unitary Coherent Particle Filter (UCPF) and Temporal Restricted Boltzmann Machine, which was able to learn to navigate around small test environments. However it was implemented in serial software, which becomes very slow as the environments and numbers of neurons scale up. Modern GPUs can parallelize execution of neural networks. The present Neural Software Engineering study develops a GPU accelerated version of the UCPF hippocampus software, using the formal Software Engineering techniques of profiling, optimisation and test-driven refactoring. Results show that the model can greatly benefit from parallel execution, which may enable it to scale from toy environments and applications to real-world ones such as self-driving car navigation. The refactored parallel code is released to the community as open source software as part of this publication.

关键词： Graphics processing unit

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