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Towards Reliable AI applications via Algorithm-Based Fault Tolerance on NVDLA 18

Towards Reliable AI Applications via Algorithm-Based Fault T...

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18th IEEE international conference on Mobility, Sensing and Networking (MSN)

作者： Sanic, Mustafa Tarik Guo, Cong Leng, Jingwen Guo, Minyi Ma, Weiyin Shanghai Jiao Tong Univ Comp Sci & Engn Shanghai Peoples R China Nanjing Med Univ Biomed Engn & Informat Nanjing Peoples R China

ISBN: (纸本)9781665464574

With the development of deep neural networks (DNNs), more complex accelerators have been designed for more sophisticated networks. Naturally, the complexity of accelerators makes them vulnerable to transient errors. Also, some DNN accelerators are widely used the safety-critical systems, such as autonomous vehicles. Therefore, the susceptibility to transient errors makes research on mitigation techniques more significant, and errors of accelerators should be limited to none. Some researchers proposed the modular redundancy method, which offers a highly reliable way but also considerably increases overhead. In this regard, algorithm-based solutions offer cheaper solutions. However, their implementation is primarily observed in software-based error injections. In this study, we propose a novel approach that focuses on implementing algorithm-based error detection (ABED) for RTL-level (hardware-based) error injections. Previous studies generally focused on the impact of soft errors in memory structures of embedded system-based accelerators. However, the main goal of this research is to study the impact of soft errors in processing elements and how to mitigate them. We implement an algorithm-based error detection that utilizes checksums for verifying convolution operations with low overhead. We first explain how to overcome the challenges of implementing ABED on FPGA-based accelerators, then how to implement it. We implement and evaluate our solution on an industry-level DNN accelerator called NVIDIA deep learning accelerator (NVDLA). In this study, our error injection method is constructed to test the most common soft error scenarios in processing units. The results of the research show that algorithm-based fault tolerance can detect all silent data corruptions (SDC) while maintaining a very low overhead (6-23%) on runtime.

关键词： NVDLA RTL AI embedded systems resilience soft error

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An Integrated MPI and OpenMP Approach for Plasma Dynamics Simulations

An Integrated MPI and OpenMP Approach for Plasma Dynamics Si...

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Computing, Semiconductor, Mechatronics, Intelligent Systems and Communications (COSMIC), international conference on

作者： Yellaboina Mani Prakash Girish K K Lalit Verma Shivam Kumar Biswajit Bhowmik Dept. of Computer Science and Engineering Maharshi Sushrut CAS Lab BRICS Laboratory National Institute of Technology Karnataka Mangalore Bharat Dept. of Computer Science and Engineering Ishwarchandra Vidyasagar AIT Lab BRICS Laboratory National Institute of Technology Karnataka Mangalore Bharat

ISBN: (数字)9798331517892

ISBN: (纸本)9798331517908

Plasma dynamics is the behavior exhibited by two or more charged species with respect to electric or magnetic fields. In high-performance computing (HPC) applications, it requires all these factors: the accuracy of parallel implementations, effective inter-process communication, and scalability with respect to workload. This paper points out the limitations in the current approaches to the plasma dynamics problems, and discusses the use of MPI continuation tasks and of its performance enhancement with OpenMP methods. Within the framework of the Vlasov-Poisson system, we develop theory of MPI continuation and describe techniques optimal for its use, which allows to efficiently combine communication with computation, which is quite a difficult task in most of the cases, especially in the case of multidimensional simulations. The results allow better insights on how to increase the level of parallelism and reduce the time to compute, which in turn fosters the formulation of more effective high-performance strategies and also the understanding of the parallelism in plasma simulations using the MPI standard.

关键词： Adaptation models Computational modeling Scalability High performance computing parallel processing Mathematical models Plasmas Computational efficiency Standards Load modeling

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Ontological Data Replication in a distributed Real-Time Database System 20

Ontological Data Replication in a Distributed Real-Time Data...

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20th international conference on New Trends in Intelligent Software Methodologies, Tools and techniques (SoMeT)

作者： Ben Abid, Wided Ben Ahmed Mhiri, Mohamed Bouazizi, Emna Gargouri, Faiez Univ Sfax Higher Inst Comp Sci & Multimedia Lab MIRACL BP 242 Sfax 3021 Tunisia Jeddah Univ Coll Comp Sci & Engn Jeddah Saudi Arabia

ISBN: (纸本)9781643681955;9781643681948

The massive use of ontologies generates a large amount of semantic data. To facilitate their management, persistent solutions for storing and querying these semantic data loads have been proposed. This gave rise to a new type of databases, called ontology-based databases (OBDB). In recent years, the need for data and real-time services has increased significantly in a large number of applications. However, the OBDB does not implement any mechanism to address real-time applications which are characterized, not only by handling large amounts of data, but also by temporal constraints, to which can be submitted data and treatments. As well, geographically extended applications, requiring using real-time databases that manage data and distributed processing are increasingly *** applications are managed by distributed Real-Time DataBase Management System (DRT-DBMS). Like any system, the DRTDBMS, often go through overload phases, due to the unpredictable arrival of transactions submitted by users. In order to better manage Quality of Service (QoS) in these systems by facing instability periods, approaches based on distributed Feedback Control Scheduling (DFCS) were proposed. These approaches does not address the use of ontological data. In this paper, we propose an approach aiming to enhance QoS in DRTDBMS based on data replication. It consists in extending the DFCS architecture by the manipulation of ontological data as well as handling the execution of accessing transactions. In the extension we propose, we study the applicability of different data replication policies. The proposed architecture is then called Replication-Based-distributed Feedback Control Scheduling Architecture for Real-Time Ontology (Replication-Based-DFCS-RTO). We also show the contribution provided by our approach through simulation results.

关键词： DRTDBMS QoS feedback control semi-total replication partial replication real-time ontology

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Multiplier Free FIR Filter Design using Array Product Generator and Multiplexer

Multiplier Free FIR Filter Design using Array Product Genera...

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international conference of Electronics, Communication and Aerospace Technology (ICECA)

作者： G Prasanna Kumar Md. Abdul Mujeer Mujaheed K Srinivas Dept. of ECE Vishnu Institute of Technology Bhimavaram India

ISBN: (数字)9798350367904

ISBN: (纸本)9798350367911

The FIR filters are widely used in various fields of applications. FPGA implementation of FIR filter has a challenge of complexity and delay. This research study mainly concentrates on the FIR filter design using less resources on the FPGA. The main units in the FIR filter are adders and multipliers, so in order to optimize the overall hardware usage, we proposed a multiplier free design because multipliers are more complex. In general, systems are making their way for less power consumption, less hardware complexity, and less area design. The proposed system is a multiplier free unit; hence, there will be few resources to be utilized as mentioned above. Multiplexer (mux)-based computation sharing approaches and actions, such as memory access operations, distributed arithmetic techniques, and common subexpression sharing, are the operations that are shared commonly. Shift and add operations can be seen extensively in the system. Those are the operations used in the array product generator for the fundamental generation of coefficients, irrespective of multipliers. In contrast to conventional multiplexer (MUX)based approaches, the given structure significantly reduces hardware complexity. The concept of sharing the similar operations for all the filter weights offers potential enhancements to MUX-based filter techniques and multiplierless scenarios, improving the power efficiency of the system and making the circuit design in an easier way. This design becomes ideal for many less power consuming applications.

关键词： Multiplexing Power demand Finite impulse response filters Hardware Generators Complexity theory Delays Field programmable gate arrays Optimization Pipeline processing

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Efficient Task-Mapping of parallel applications Using a Space-Filling Curve 22

Efficient Task-Mapping of Parallel Applications Using a Spac...

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Proceedings of the international conference on parallel Architectures and Compilation techniques

作者： Oh-Kyoung Kwon Ji-hoon Kang Seungchul Lee Wonjung Kim Junehwa Song Korea Advanced Institute of Science and Technology Daejeon Republic of Korea Korea Institute of Science and Technology Information Daejeon Republic of Korea

ISBN: (纸本)9781450398688

Improving the communication performance of parallel programs is an important but difficult problem in a large-scale distributed memory-based cluster. Efforts to improve parallel scalability often face severe huddles in managing communication overheads. This paper proposes a framework of a space-filing curve(SFC)-based task-remapping for communication intensive parallel applications. An SFC-based mapping, when applied for task-mapping of parallel applications preserves locality in terms of communications and produce a less fragmented task-mapping, reducing communication overheads. The framework also provides tools for performance analysis to see if the proposed task-mapping is appropriate for a given application running on a target system. It further develops a binary classifier as a predictor to decide whether or not to apply the proposed mapping before run-time. We evaluate the framework with three communication intensive applications in Cartesian coordinates: P3DFFT solver and Channel code using 2D domain decomposition model, and Poisson solver using 3D domain decomposition. The evaluation is conducted on a large-scale cluster system of fat-tree topology with up to 1,024 compute nodes. The proposed task-mapping achieves the overall performance improvement ranging from ~30% to ~66% over the baseline approach depending on the workloads. Also, when used in combination with the binary classifier-based predictor, it achieves the expected performance gains from 4% to 8%.

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Generalizing Functional Error Correction for Language and Vision-Language Models

Generalizing Functional Error Correction for Language and Vi...

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international conference on Machine Learning and applications (ICMLA)

作者： Wenyu Peng Simeng Zheng Michael Baluja Tao Xie Anxiao Jiang Paul H. Siegel Electrical and Computer Engineering Department University of California San Diego La Jolla CA USA Computer Science San Diego State University San Diego CA USA Department of Computer Science and Engineering Texas A&M University College Station TX USA

ISBN: (数字)9798350374889

ISBN: (纸本)9798350374896

The goal of functional error correction is to preserve neural network performance when stored network weights are corrupted by noise. To achieve this goal, a selective protection (SP) scheme was proposed to optimally protect the functionally important bits in binary weight representations in a layer-dependent manner. Although it showed its effectiveness in image classification tasks on some relatively simple networks such as ResNet-18 and VGG-16, it becomes inadequate for emerging complex machine learning tasks generated from natural language processing and vision-language association domains. To solve this problem, we extend the SP scheme in three directions: task complexity, model complexity, and storage complexity. Extensions to complex natural language and vision-language tasks include text categorization and “zero-shot” textual classification of images. Extensions to more complex models with deeper block structures and attention mechanisms consist of Very Deep Convolutional Neural Network (VDCNN) and Contrastive Language-Image Pre-Training (CLIP) networks. Extensions to more complex storage configurations focus on distributed storage architectures to support model parallelism. Experimental results show that the optimized SP scheme preserves network performance in all of these settings. The results also provide insights into redundancy-performance tradeoffs, generalizability of SP across datasets and tasks, and robustness of partitioned network architectures.

关键词： Adaptation models Text categorization Neural networks Noise parallel processing Network architecture Robustness Error correction Complexity theory Protection

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Scalable and Flexible High-Performance In-Network processing of Hash Joins in distributed Databases 20

Scalable and Flexible High-Performance In-Network Processing...

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20th international conference on Field-Programmable Technology (ICFPT)

作者： Wirth, Johannes Hofmann, Jaco A. Thostrup, Lasse Binnig, Carsten Koch, Andreas Tech Univ Darmstadt Embedded Syst & Applicat Grp Darmstadt Germany Tech Univ Darmstadt Data Management Lab Darmstadt Germany

ISBN: (纸本)9781665420105

Programmable switches allow to offload specific processing tasks into the network and promise multi-Tbit /s throughput. One major goal when moving computation to the network is typically to reduce the volume of network traffic, and thus improve the overall performance. In this manner, programmable switches are increasingly used, both in research as well as in industry applications, for various scenarios, including statistics gathering, in-network consensus protocols, and more. However, the currently available programmable switches suffer from several practical limitations. One important restriction is the limited amount of available memory, making them unsuitable for stateful operations such as Hash Joins in distributed databases. In previous work, an FPGA-based In-Network Hash Join accelerator was presented, initially using DDR-DRAM to hold the state. In a later iteration, the hash table was moved to on-chip HBM-DRAM to improve the performance even further. However, while very fast, the size of the joins in this setup was limited by the relatively small amount of available HBM. In this work, we heterogeneously combine DDR-DRAM and HBM memories to support both larger joins and benefit from the far faster and more parallel HBM accesses. In this manner, we are able to improve the performance by a factor of 3x compared to the previous HBM-based work. We also introduce additional configuration parameters, supporting a more flexible adaptation of the underlying hardware architecture to the different join operations required by a concrete use-case.

关键词： HBM FPGA Hash Join INP In-Network processing

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Accelerating Matrix Power Operations with GPUs 2021

Accelerating Matrix Power Operations with GPUs

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4th international conference on Electronics, Communications and Control Engineering (ICECC)

作者： Wu, Lezhou Northeastern Univ Coll Informat Sci & Engn Shenyang 110819 Liaoning Peoples R China

ISBN: (纸本)9781450389129

Many-core framework, represented by Graphic processing Unit (GPU), has been becoming more popular in scientific computing and data analysis, and Compute Unified Device Architecture (CUDA) allows developers to carry out computation on GPUs more conveniently. Matrix operation is one of the most important application scenarios of GPU computation and CUDA, widely appearing in domains like graph applications and artificial intelligence. This paper focuses on accelerating matrix power operation (MPO) process, which appears in many engineering problems and may be time-consuming when the scale of matrixes is large, with GPUs and CUDA. In this paper, three techniques are used to speed up the MPO process: matrix parallel reduction, matrix parallel multiplication and CUDA dynamic parallelism. The experiments were carried out on NVIDIA RTX 2080 Super and Intel(R) Core(TM) i7-10750H. The code is compiled and executed in Visual Studio 2019 community, the GPU driver version is 461.40, the CUDA version is 11.1, and the NVCC version is 11.1.74. With all three techniques, the MPO process can get hundreds of times speedup compared with the sequential multiplication process executed by Eigen library, even though the code of algorithm is hardly optimized. Moreover, with the number of power increasing, the efficiency of algorithm can be even higher because of the relatively fixed time consumed in data transmission and GPU memory allocation.

关键词： GPU CUDA Matrix power operation parallel reduction Dynamic parallelism Matrix parallel multiplication

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Adversarial Attack and Defense for Transductive Support Vector Machine

Adversarial Attack and Defense for Transductive Support Vect...

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international Joint conference on Neural Networks (IJCNN)

作者： Li Liu Haiyan Chen Changchun Yin Liming Fang College of Computer Science and Technology Nanjing University of Aeronautics and Astronautics China Science and Technology on Parallel and Distributed Processing Laboratory (PDL) China

ISBN: (数字)9798350359312

ISBN: (纸本)9798350359329

As a classic semi-supervised approach, the Transductive Support Vector Machine (TSVM) has exhibited remarkable accuracy by utilizing unlabeled data. However, the robustness of TSVM against adversarial attacks remains a subject of investigation, prompting concerns about its reliability in security-critical applications. To unveil the vulnerability of TSVM, we introduce a finite-attack model specifically tailored to its characteristics, effectively manipulating its outputs. Additionally, we present Adversarial Defense-based TSVM (AD-TSVM), the first dedicated defense scheme designed for TSVM. AD-TSVM incorporates adversarial information into the optimization process, enhancing robustness by rebuilding a customized loss function and decision margin to counteract attacks. Rigorous experiments conducted on benchmark datasets demonstrate the effectiveness of AD-TSVM in significantly improving both the accuracy and stability of TSVM when confronted with adversarial attacks. This pioneering research assesses the weaknesses of TSVM and, more importantly, offers valuable insights and solutions for developing secure and trustworthy TSVM systems in the face of emerging threats.

关键词： Training Support vector machines Accuracy Machine learning algorithms Neural networks Robustness Vectors

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Config 2.0: Towards reinforcement learning based configuration of stream processing systems 21

Config 2.0: Towards reinforcement learning based configurati...

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22nd international Middleware conference, Middleware 2021

作者： Tahir, Jawad Technical University of Munich Garching Germany

ISBN: (纸本)9781450391559

distributed stream processing systems (DSPSs) have enabled us to build scalable, fast, and reactive applications. As faults are common in any distributed system, DSPSs allow for recovering from faults using various techniques, for example, snapshotting their state on a key-value (KV) store and then replaying the events in case of a failure. The performance of the recovery process is dependent on the workload, configuration of the DSPS and performance of the KV store. Performance tuning of a KV store is a notoriously difficult job. In this thesis proposal, we propose a reinforcement learning (RL) based agent which configures the DSPS and the KV store under varying workloads to minimize the impact of a failure on the performance. © 2021 ACM.

关键词： Fault tolerance

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