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Improving Efficiency in Large-Scale Decentralized distributed Training

Improving Efficiency in Large-Scale Decentralized Distribute...

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IEEE international conference on Acoustics, Speech, and Signal processing (ICASSP)

作者： Mang, Wei Cui, Xiaodong Kayi, Abdullah Liu, Mingrui Finkler, Ulrich Kingsbury, Brian Saon, George Mroueh, Youssef Buyuktosunoglu, Alper Das, Payel Kung, David Picheny, Michael IBM Res Yorktown Hts NY 10598 USA Univ Iowa Iowa City IA USA

ISBN: (纸本)9781509066315

Decentralized parallel SGD (D-PSGD) and its asynchronous variant Asynchronous parallel SGD (AD-PSGD) is a family of distributed learning algorithms that have been demonstrated to perform well for large-scale deep learning tasks. One drawback of (A)D-PSGD is that the spectral gap of the mixing matrix decreases when the number of learners in the system increases, which hampers convergence. In this paper, we investigate techniques to accelerate (A)D-PSGD based training by improving the spectral gap while minimizing the communication cost. We demonstrate the effectiveness of our proposed techniques by running experiments on the 2000-hour Switch-board speech recognition task and the ImageNet computer vision task. On an IBM P9 supercomputer, our system is able to train an LSTM acoustic model in 2.28 hours with 7.5% WER on the Hub5-2000 Switchboard (SWB) test set and 13.3% WER on the CallHome (CH) test set using 64 V100 GPUs and in 1.98 hours with 7.7% WER on SWB and 13.3% WER on CH using 128 V100 GPUs, the fastest training time reported to date.

关键词： distributed training decentralized SGD parallel computing automatic speech recognition image recognition

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Enhancing Load-Balancing of MPI applications with Workshare 27th

Enhancing Load-Balancing of MPI Applications with Workshare

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27th international European conference on parallel and distributed Computing (Euro-Par)

作者： Dionisi, Thomas Bouhrour, Stephane Jaeger, Julien Carribault, Patrick Perache, Marc Exascale Comp Res Lab 2 Rue Piquetterie F-91680 Bruyeres Le Chatel France CEA DAM DIF F-91297 Arpajon France Univ Paris Saclay CEA Lab Informat Haute Performance Calcul & Simulat F-91680 Bruyeres Le Chatel France

ISBN: (纸本)9783030856656;9783030856649

Some high-performance parallel applications (e.g., simulation codes) are, by nature, prone to computational imbalance. With various elements, such as particles or multiple materials, evolving in a fixed space (with different boundary conditions), an MPI process can easily end up with more operations to perform than its neighbors. This computational imbalance causes performance loss. Load-balancing methods are used to limit such negative impacts. However, most load-balancing schemes rely on shared-memory models, and those handling MPI load-balancing use too much heavy machinery for efficient intra-node load-balancing. In this paper, we present the MPI Workshare concept. With MPI Workshare, we propose a programming interface based on directives, and the associated implementation, to leverage light MPI intranode load-balancing. In this work, we focus on loop worksharing. The similarity of our directives with OpenMP ones makes our interface easy to understand and to use. We provide an implementation of both the runtime and compiler directive support. Experimental results on well-known mini-applications (MiniFE, LULESH) show that MPI Workshare succeeds in maintaining the same level of performance as well-balanced workloads even with high imbalance parameter values.

关键词： Application programming interfaces (API)

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Interface Entity based Architecture for Efficient Query processing in Mobile Networks 5

Interface Entity based Architecture for Efficient Query Proc...

引用

5th international conference on Computing Methodologies and Communication, ICCMC 2021

作者： Patil, Kshitija R. Patil, Vinod M. H.V.P.M. D. C. P. E. Department of Computer Science Amravati Maharashtra India Shri Shivaji College Department of Computer Science Akola Maharashtra India

ISBN: (纸本)9781665403603

In Mobile computing environment, the distributed approach of the system faces the commonly occurred limitations like disconnections caused due to mobility, low bandwidth of wireless channels, restricted battery power and lack of consistent stable storage on mobile nodes which results in bad performance of mobile computing applications. While implementing query processing system in mobile environment it is necessary to consider related issues that may delay the processing. It is needed to process the query based on the current location of the mobile device. It is needful to handle it energy efficiently. The use of Interface Entity proves helpful for designing intelligent query processing architecture where the proposed query processing technique is one of the techniques in which the caching data at Interface Entity proved as a powerful mechanism. It can provide fault tolerance by improving performance of query processing. The caching is applied for frequently accessed data at the mobile clients. Thus caching improves the efficiency and reliability of data delivery over the network. The IQPA proves to be suitable for less as well as large number of nodes in terms of improved throughput, packet delivery ratio and less packet loss. © 2021 IEEE.

关键词： Query processing

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Signal processing Based Method for Real-Time Anomaly Detection in High-Performance Computing

Signal Processing Based Method for Real-Time Anomaly Detecti...

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IEEE Annual international Computer Software and applications conference (COMPSAC)

作者： Arunavo Dey Tanzima Islam Chase Phelps Christopher Kelly Department of Computer Science Texas State University San Marcos TX Brookhaven National Laboratory Computer Science Initiative Long Island NY

Performance anomalies can manifest as irregular execution times or abnormal execution events for many reasons, including network congestion and resource contention. Detecting such anomalies in real-time by analyzing the details of performance traces at scale is impractical due to the sheer volume of data High-Performance Computing (HPC) applications produce. In this paper, we propose formulating HPC performance anomaly detection as a signal-processing problem where anomalies can be treated as noise. We evaluate our proposed method in comparison with two other commonly used anomaly detection techniques of varying complexity based on their detection accuracy and scalability. Since real-time in-situ anomaly detection at a large scale requires lightweight methods that can handle a large volume of streaming data, we find that our proposed method provides the best trade-off. We then implement the proposed method in Chimbuko, the first online, distributed, and scalable workflow-level performance trace analysis framework. We compare our proposed signal-based anomaly detection algorithm with two other methods using a function of their accuracy, F1 score, and detection overhead. Our experiments demonstrate that our proposed approach achieves a 99% improvement for the benchmark datasets and a 93% improvement with Chimbuko traces.

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Compiler-Directed Incremental Checkpointing for Low Latency GPU Preemption

Compiler-Directed Incremental Checkpointing for Low Latency ...

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international Symposium on parallel and distributed processing (IPDPS)

作者： Zhuoran Ji Cho-Li Wang Department of Computer Science The University of Hong Kong Hong Kong China

GPUs are widely used in data centers to accelerate data-parallel applications. The multiuser and multitasking environment provides a strong incentive for preemptive GPU multitasking, especially for latency-sensitive jobs. Due to the large contexts of GPU kernels, preemptive GPU context switching is costly. Many novel GPU preemption techniques are proposed. Among them, checkpoint-based GPU preemption enables low latency GPU preemption but incurs a high runtime overhead. Prior studies propose to exclude dead registers from the checkpoint file to reduce the runtime overhead. It works well for CPUs, but it is not rare that a live register is not updated between two checkpoints for GPU kernels. This paper presents TripleC, a compiler-directed incremental checkpointing technique specially designed for GPU preemption. It further excludes the registers, which have not been overwritten since the last time they were spilled, from the checkpoint file with data flow analysis. The checkpoint placement algorithm of TripleC can properly estimate a checkpoint's cost under incremental checkpointing. It also considers the interaction among checkpoints so that the overall cost is minimized. Moreover, TripleC relaxes the conventional checkpointing constraint that the whole register context must be spilled before passing the checkpoint. Because of the diverse control flow, placing a register spilling instruction at different points incurs different costs. TripleC minimizes the cost with a two-phase algorithm that schedules these register spilling instructions at compilation time. Evaluations show that TripleC reduces the runtime overhead by 12.9 % on average compared with the state-of-the-art non-incremental checkpointing approach.

关键词： Checkpointing Schedules Costs Runtime Graphics processing units Switches Multitasking

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Voltage Island-Aware Energy-Efficient Scheduling of parallel Streaming Tasks on Many-Core CPUs 28

Voltage Island-Aware Energy-Efficient Scheduling of Parallel...

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28th Euromicro international conference on parallel, distributed and Network-Based processing (PDP)

作者： Melot, Nicolas Kessler, Christoph Keller, Joerg Linkoping Univ S-58183 Linkoping Sweden Fernuniv D-58084 Hagen Germany

ISBN: (纸本)9781728165820

For multi- and many-core CPUs, dynamic voltage and frequency scaling (DVPS) for individual cores provides an effective way for energy-efficient execution of applications. However, this requires additional hardware within the chip that regulates voltage and frequency for each hardware sub-component that can be scaled separately. Because of the significant cost of this control hardware, it is often not realistic to provide such a regulator for each individual core. Instead, chip manufacturers group cores into islands consisting of multiple cores with a common regulator, and energy optimizing solutions must lake this constraint into account when assigning frequencies 10 jobs and cores. Crown Scheduling is a technique for the combined resource allocation, mapping and discrete DVFS-level selection for actor networks consisting of moldable parallel streaming tasks for energy efficient execution given a throughput constraint. We extend crown scheduling to compute correct schedules also in the presence of DVFS islands constraints. We find that, for most task sets, the crown scheduler computes almost equally good schedules for target architectures with and without island constraints.

关键词： static scheduling energy-efficient execution optimization algorithm

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Privacy Preserving Ensemble Learning Classification Model for Mental Healthcare

Privacy Preserving Ensemble Learning Classification Model fo...

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international conference on parallel distributed and Grid Computing (PDGC)

作者： Nisha Chaudhary Vidushi Gupta Kanav Sandhir Rishabh Gupta Sakshi Chhabra Ashutosh Kumar Singh Department of Computer Applications NIT Kurukshetra Haryana India Department of Computer Applications PIET Panipat Haryana India

ISBN: (纸本)9781665454025

Privacy protection technology can effectively handle personal data to prevent the leakage of sensitive information during data publishing and data analysis. Countless research analysis on facilitating privacy-preserving data collection has been conducted through the years. Medical research represents an important application that is necessary to extract useful information and protect patient privacy One of the main techniques recently used is ensemble learning. In contrast to ordinary approaches, which try to learn one hypothesis from a training dataset, ensemble learning tries to construct a set of hypotheses and combine them. This strategy is primarily used to improve the performance of the model, but the major restraint of this approach is that multiple parties cannot share their data extracted from the ensemble learning model with a privacy guarantee; therefore, it is a great demand to develop privacy-preserving collaborative ensemble learning. In this paper, introducing a differential privacy-based ensemble learning classification model while maintaining its utility and accuracy, which will evaluate the medical health record and classify the patient’s medical illness from the given data in a way that requires very little human participation from doctors. The proposed model has lower time and money costs associated and will provide assistance to medical practitioners.

关键词： Training Privacy Data privacy Publishing Medical services Predictive models Grid computing

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parallel N-Body Performance Comparison: Julia, Rust, and More 30th

Parallel N-Body Performance Comparison: Julia, Rust, and Mo...

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30th international conference on parallel and distributed processing techniques, PDPTA 2024, held as part of the World Congress in Computer Science, Computer Engineering and Applied Computing, CSCE 2024

作者： Lewis, Mark C. Garcia, Clarissa Tollett, Audrey Aguirre, Seven Hafner, Henry McMahon, John Sickafoose, Amanda A. Trinity University San AntonioTX78212 United States Planetary Science Institute TucsonAZ85719 United States

ISBN: (纸本)9783031856372

This paper explores parallelism performance for C, C++, Go, Java, Julia, and Rust on N-body simulations. We begin with a basic O(N2) simulation for each language based on the n-body benchmark in the Benchmark Game. The original benchmark is adjusted to include a larger number of particles and run in parallel. We also add parallelism to the force calculations using a kD-tree. This work builds on previous work by including parallelism and adding the Julia programming language to our survey. We find that for straight number-crunching, all of these languages provide similar performance, and all have sufficient support for parallelism that runtimes scale well with thread counts. On the other hand, when a spatial data structure, such as the kD-tree, is introduced, the runtimes vary dramatically between languages. In that situation, Julia’s performance looks more like Python, taking over 100 times as long as Rust/C/C++ to finish. Rust comes out on top with an impressive 50% lead over C and C++. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： C++ (programming language)

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Review of Hardware Implementations of Convolution for Discrete Wavelet Transform

Review of Hardware Implementations of Convolution for Discre...

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North Karnataka Subsection Flagship international conference (NKCon), IEEE

作者： Ramprakash C Skanda Prasad Pratyusha R Raghu Jayaramu Department of Electronics and Communication Engineering The National Institute of Engineering Mysuru India

Field programmable gate arrays (FPGAs) have often been used as hardware accelerators for digital signal processing (DSP) algorithms such as convolution and filtering operations. This work is a review of hardware implementations of the convolution operation specific to the discrete wavelet transform (DWT). For such applications, read-only memory (ROM)-based architectures are known for their speed and performance. Two such architectures-distributed arithmetic (DA) and residue number system (RNS) are reviewed. Hardware utilization of both architectures using similar inputs and parameters on the Digilent Nexys-A7-100T field programmable gate array (FPGA) platform using Xilinx Vivado and other open-source tools are reported. distributed arithmetic (DA) is found to be favourable for small input lengths, but residue number system (RNS) will surpass it for larger input lengths. A parallel distributed arithmetic (DA) implementation is also implemented, that offers significant computational speed-up at minimal power cost.

关键词： Convolution Signal processing algorithms Computer architecture Transforms Digital signal processing Logic gates Discrete wavelet transforms

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Data Integration, Cleaning, and Deduplication: Research Versus Industrial Projects 24th

Data Integration, Cleaning, and Deduplication: Research Vers...

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24th international conference on Information Integration and Web Intelligence (iiWAS)

作者： Wreinbel, Robert Poznan Univ Tech Poznan Poland

ISBN: (纸本)9783031210464;9783031210471

In business applications, data integration is typically implemented as a data warehouse architecture. In this architecture, heterogeneous and distributed data sources are accessed and integrated by means of Extract-Transform-Load (ETL) processes. Designing these processes is challenging due to the heterogeneity of data models and formats, data errors and missing values, multiple data pieces representing the same realworld objects. As a consequence, ETL processes are very complex, which results in high development and maintenance costs aswell as long runtimes. To ease the development of ETL processes, various research and technological solutions were development. They include among others: (1) ETL design methods, (2) data cleaning pipelines, (3) data deduplication pipelines, and (4) performance optimization techniques. In spite of the fact that these solutions were included in commercial (and some open license) ETL design environments and ETL engines, there still exist multiple open issues and the existing solutions still need to advance. In this paper (and its accompanying talk), I will provoke a discussion on what problems one can encounter while implementing ETL pipelines in real business (industrial) projects. The presented findings are based on my experience from research and commercial data integration projects in financial, healthcare, and software development sectors. In particular, I will focus on a few particular issues, namely: (1) performance optimization of ETL processes, (2) cleaning and deduplicating large row-like data sets, and (3) integrating medical data.

关键词： Data integration Data warehouse Data lake Big data Extract transform load Data processing workflow Data processing pipeline Data quality Data deduplication ETL performance optimization

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