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Analysis of Real-Time Hostile Activitiy Detection from Spatiotemporal Features Using Time distributed Deep CNNs, RNNs and Attention-Based Mechanisms

Analysis of Real-Time Hostile Activitiy Detection from Spati...

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international Image processing, applications and Systems conference (IPAS)

作者： Labib Ahmed Siddique Rabita Junhai Tanzim Reza Salman Sayeed Khan Tanvir Rahman Department of Computer Science and Engineering BRAC University Dhaka Bangladesh Department of Computer and Information Sciences College of Engineering University of Delaware

ISBN: (纸本)9781665462204

Real-time video surveillance, through CCTV camera systems has become essential for ensuring public safety which is a priority today. Although CCTV cameras help a lot in increasing security, these systems require constant human interaction and monitoring. To eradicate this issue, intelligent surveillance systems can be built using deep learning video classification techniques that can help us automate surveillance systems to detect violence as it happens. In this research, we explore deep learning video classification techniques to detect violence as they are happening. Traditional image classification techniques fall short when it comes to classifying videos as they attempt to classify each frame separately for which the predictions start to flicker. Therefore, many researchers are coming up with video classification techniques that consider spatiotemporal features while classifying. However, deploying these deep learning models with methods such as skeleton points obtained through pose estimation and optical flow obtained through depth sensors, are not always practical in an IoT environment. Although these techniques ensure a higher accuracy score, they are computationally heavier. Keeping these constraints in mind, we experimented with various video classification and action recognition techniques such as ConvLSTM, LRCN (with both custom CNN layers and VGG-16 as feature extractor) CNNTransformer and C3D. We achieved a test accuracy of 80% on ConvLSTM, 83.33% on CNN-BiLSTM, 70% on VGG16-BiLstm, 76.76% on CNN-Transformer and 80% on C3D.

关键词： Deep learning Streaming media Feature extraction Cameras Video surveillance Real-time systems Skeleton

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A neuro-genetic approach for inferring gene regulatory networks from gene expression data 22

A neuro-genetic approach for inferring gene regulatory netwo...

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Proceedings of the 9th international conference on Bioinformatics Research and applications

作者： Guo Mao Zhengbin Pang Jie Liu Ke Zuo Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology China

ISBN: (纸本)9781450396868

Accurate prediction of gene regulation rules is important for understanding complex life processes. Existing computational algorithms designed for bulk transcriptome datasets typically require a large number of time points to infer gene regulatory networks (GRNs), are suitable for a small number of genes, and cannot efficiently detect potential regulatory relationships. We propose an approach based on a deep learning framework to reconstruct GRNs from bulk transcriptome datasets, assuming that the expression levels of transcription factors involved in gene regulation are strong predictors of the expression of their target genes. The algorithm uses multilayer perceptrons to infer the regulatory relationship between multiple transcription factors and a gene, and uses genetic algorithms to search for the best regulatory gene combination. The results show that our approach is more accurate than other methods for reconstructing gene regulatory networks on real-world and simulated bulk transcriptome gene expression datasets.

关键词： gene regulatory networks datasets multilayer perceptrons genetic algorithms

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5th international conference on Intelligent Computing and applications, ICICA 2019

5th International Conference on Intelligent Computing and Ap...

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5th international conference on Intelligent Computing and applications, ICICA 2019

ISBN: (纸本)9789811555657

The proceedings contain 71 papers. The special focus in this conference is on Intelligent Computing and applications. The topics include: Performance Estimation and Analysis Over the Supervised Learning Approaches for Motor Imagery EEG Signals Classification;fully Automated Digital Mammogram Segmentation;empirical Study of Computational Intelligence Approaches for the Early Detection of Autism Spectrum Disorder;Intelligent Monitoring of Bearings Using Node MCU Module;image Denoising Using Various Image Enhancement techniques;energy Consumption Analysis and Proposed Power-Aware Scheduling Algorithm in Cloud Computing;relationship Between Community Structure and Clustering Coefficient;digital Image Forensics-Image Verification techniques;energy Efficient Data Centre Selection Using Service Broker Policy;using Automated Predictive Analytics in an Online Shopping Ecosystem;design and Development of Home Automation System;performance Analysis Study of Stochastic Computing Based Neuron;Scheduling of parallel Tasks in Cloud Environment Using DAG MODEL;GREENIE—Smart Home with Smart Power Transmission;ANAVI: Advanced Navigation Assistance for Visually Impaired;THIRD EYE—Shopfloor Data processing and Visualization Using Image Recognition;A Hybrid Search Group Algorithm and Pattern Search Optimized PIDA Controller for Automatic Generation Control of Interconnected Power System;Fractional Order PID Controlled PV Fed Quadratic Boost Converter TZ Source Inverter Fed Permanent Magnet Brushless Motor Drive;co-ordinate Measurement of Roll-Cage Using Digital Image processing;peformance Analysis of Joysticks Used in Infotainment Control System in Automobiles;Probabilistic Principal Component Analysis (PPCA) Based Dimensionality Reduction and Deep Learning for Cancer Classification;blockchain Technology for Data Sharing in Decentralized Storage System;Understanding Concepts of Blockchain Technology for Building the DApps;chennai Water Crisis—Data Analysis.

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Introducing a Stream processing Framework for Assessing parallel Programming Interfaces

Introducing a Stream Processing Framework for Assessing Para...

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Euromicro conference on parallel, distributed and Network-Based processing

作者： Adriano Marques Garcia Dalvan Griebler Luiz G. L. Fernandes Claudio Schepke School of Technology Pontifical Catholic University of Rio Grande do Sul (PUCRS) Porto Alegre Brazil Laboratory of Advanced Research on Cloud Computing (LARCC) Três de Maio Maio Faculty (SETREM) Três de Maio Brazil Federal University of Pampa (UNIPAMPA) Alegrete Brazil

Stream processing applications are spread across different sectors of industry and people's daily lives. The increasing data we produce, such as audio, video, image, and text are demanding quickly and efficiently computation. It can be done through Stream parallelism, which is still a challenging task and most reserved for experts. We introduce a Stream processing framework for assessing parallel Programming Interfaces (PPIs). Our framework targets multi-core architectures and C++ stream processing applications, providing an API that abstracts the details of the stream operators of these applications. Therefore, users can easily identify all the basic operators and implement parallelism through different PPIs. In this paper, we present the proposed framework, implement three applications using its API, and show how it works, by using it to parallelize and evaluate the applications with the PPIs Intel TBB, FastFlow, and SPar. The performance results were consistent with the literature.

关键词： Industries parallel programming distributed databases Computer architecture Streaming media parallel processing Task analysis

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Highly Efficient and GPU-Friendly Implementation of BFS on Single-node System 18

Highly Efficient and GPU-Friendly Implementation of BFS on S...

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18th IEEE Int Symp on parallel and distributed Proc with Applicat (ISPA) / 10th IEEE Int Conf on Big Data and Cloud Comp (BDCloud) / IEEE Int Symp on Social Comp and Networking (SocialCom) / IEEE Int Conf on Sustainable Comp and Commun (SustainCom)

作者： Dong, Rongyu Cao, Huawei Ye, Xiaochun Zhang, Yuan Hao, Qinfen Fan, Dongrui Chinese Acad Sci Inst Comp Technol State Key Lab Comp Architecture Beijing 100190 Peoples R China Univ Chinese Acad Sci Sch Comp & Control Engn Beijing 100049 Peoples R China

ISBN: (纸本)9781665414852

With the development of computer technology, the data generated in our daily life is growing rapidly. Data-intensive algorithms take more and more important part in high performance computing. The Breadth-First Search (BFS) is a typical data-intensive algorithm and characterized with intensive irregular memory access, low computation intensity and strong data dependency. Although Graphics processing Unit (GPU) offers massive parallelism, BFS is not GPU-friendly due to above characteristics. To utilize the power of GPU for BFS, efficient scheduling of massive threads and better utilization of GPU memory hierarchy are required. In this paper, we focus on highly efficient implementation of BFS on NVIDIA GPU platform. We propose three optimization techniques, including fine-grained parallelism, GPU-oriented CSR structure and vertex quick-search to overcome performance bottlenecks in GPU. Fine-grained parallelism can improve the workload balance for parallel implementation in top-down stage. GPU-oriented CSR structure employs a GPU-friendly data layout, which can improve the efficiency of memory access. Vertex quick-search is proposed to reduce redundant graph computations on GPU. Finally, we conduct extensive experiments on GPU-based platform to verify the effectiveness of these techniques. We achieve 237.94 GTEPS for the Kronecker graph with 2(26) vertices and 2(30) edges. In terms of energy efficiency, our implementation ranks 1st place on the November 2019 Green Graph500 list.

关键词： BFS parallel computing graph processing CUDA

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An Architecture- Independent CGRA Compiler enabling OpenMP applications

An Architecture- Independent CGRA Compiler enabling OpenMP A...

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IEEE international Symposium on parallel and distributed processing Workshops and Phd Forum (IPDPSW)

作者： Takuya Kojima Boma Adhi Carlos Cortes Yiyu Tan Kentaro Sano Graduate School of Information Science and Technology The University of Tokyo Tokyo Japan Center for Computational Science (R-CCS) RIKEN Kobe Japan

ISBN: (数字)9781665497473

ISBN: (纸本)9781665497480

Coarse-Grained reconfigurable architecture (CGRA) is a promising platform for HPC systems in the post-Moore's era. A single-source programming model is essential for practical heterogeneous computing. However, we do not have a canonical programming model and a frontend compiler for it. Existing versatile CGRAs, in respect to their execution model, computational capability, and system structure, magnify the difficulty of orchestrating the compiler techniques. It consequently forces designers of the CGRAs to develop the compiler from scratch, working only for their architectures. Such an approach is outdated, given other successful accelerators like GPU and FPGAs. This paper presents a new CGRA compiler framework in order to reduce development efforts of CG RA applications. OpenMP annotated codes are fed into the proposed compiler, as recent OpenMP support device offloading to the accelerators. This property improves the reusability of the existing source code for HPC workloads. The design of the compiler is inspired by LLVM, which is the most famous compiler framework so that the frontend is built to be architecture-independent. In this work, we demonstrate that the proposed compiler can handle different types of CG RAs without changing the source codes. In addition, we discuss the effect of architecture-independent optimization algorithms. We also provide an open-source implementation of the compiler framework at https://***/hal-lab-u-tokyo/CGRAOmp.

关键词： Codes Runtime Computational modeling Graphics processing units Programming Heterogeneous networks Reconfigurable architectures

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Implementation of Table-Based Cyclic Redundancy Check (CRC-32) for Gigabit Ethernet applications

Implementation of Table-Based Cyclic Redundancy Check (CRC-3...

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Emerging Technology (INCET), international conference for

作者： P. Kishore Bolli Abhinay Pal Lolakapuri Nanda Kishore Chintamreddy Venkata Revathi Electronics and Communication Engineering VNR Vignana Jyothi Institute of Engineering and Technology Hyderabad India

As the transaction data is Over 2.5 quintillion bytes per day. To transmit data between datacenters, Ethernet networks requires high speed and fast error detection techniques. High performance CRC-32 (Cyclic redundancy check) parallel architecture for Gigabit ethernet application is proposed in this work. This is a table-based approach. This is designed based on highly parallel algorithm. In this work a generating polynomial with hex value (04C11DB7) is used for generating CRC-32 value. According to this architecture a data frame’s CRC value is calculated in a divide and conquer fashion. In this work 128 bits are used as input to CRC module and respective CRC value is calculated. This architecture processes 128 bits per second. Look tables are utilized for this purpose. Around 16 lookup tables are used for this purpose. This algorithm can achieve throughput of 10 Gbps for a clock input of 83.33Mhzs speed. Higher speeds can be achieved by increasing clock speed. Further throughput can be increased by increasing number of bits processing for second. This architecture is compatible for any size of data input, but it processes 128 bits per second. 256x32 bit size of SRAM is used to store content of look up table. About 16kb SRAM is costs for storing all table contents. The proposed model is implemented in Verilog in Xilinx Vivado – 2022 tool. Further design can be extended to other CRC polynomials.

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Rammed, or What RAM³S Taught Us 22

Rammed, or What RAM<SUP>3</SUP>S Taught Us

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22nd Annual international conference on Information Integration and Web-Based applications and Services (IIWAS)

作者： Bartolini, Ilaria Patella, Marco Univ Bologna Alma Mater Studiorum Dept Comp Sci & Engn DISI Bologna Italy

ISBN: (纸本)9781450389228

RAM(3)S (Real-time Analysis of Massive MultiMedia Streams) is a framework that acts as a middleware software layer between multimedia stream analysis techniques and Big Data streaming platforms, so as to facilitate the implementation of the former on top of the latter. Indeed, the use of Big Data platforms can give way to the efficient management and analysis of large data amounts, but they require the user to concentrate on issues related to distributed computing, since their services are often too raw. The use of RAM(3)S greatly simplifies deploying non-parallel techniques to platforms like Apache Storm or Apache Flink, a fact that is demonstrated by the four different use cases we describe here. We detail the lessons we learned from exploiting RAM(3)S to implement the detailed use cases.

关键词： Stream processing Real-Time Analysis Big Data

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SOG-Based Multi-Core LTL Model Checking 18

SOG-Based Multi-Core LTL Model Checking

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作者： Abid, Chiheb Ameur Klai, Kais Arias, Jaime Ouni, Hiba Univ Carthage Tunis SupCom Mediatron Lab Tunis Tunisia Univ Sorbonne Paris North CNRS UMR 7030 LIPN Villetaneuse France

ISBN: (纸本)9781665414852

The model checking is one of the major techniques used in the formal verification. This technique builds on an automatic procedure that takes a model M of a system and a formula phi expressing a temporal property, and decides whether the system satisfies the property (denoted by M satisfies phi). The model checking technique is based on an exhaustive exploration of the state space of the system and, thus suffers from the state space explosion problem: it can happen that the verification process stops because of lack of time or space. Among the existing solutions to tackle this problem the Symbolic Observation Graph (SOG) has been proposed as a reduced representation of the reachability graph preserving linear temporal logic properties (LTL) i.e. checking an LTL property on the SOG is equivalent to check it on the original state space. The parallel construction of the SOG could increase the speedup and scalability of model checking. In this paper, we propose a new model checking algorithm built on a parallel construction of the SOG. The SOG is adapted to allow the preservation of both state and event-based LTL formulae i.e., the atomic propositions involved in the formula to be checked could be either state-based or event-based propositions. We implemented the proposed model checking algorithm within a C++ prototype and compared our preliminary results with the state of the art model checkers.

关键词： parallel model checking Temporal Logic Decision Diagrams

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Improving parallel Exhaustive Subgroup Discovery with Early Search Space Pruning

Improving Parallel Exhaustive Subgroup Discovery with Early ...

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IEEE international conference on High Performance Computing Workshops (HiPCW)

作者： Jyoti Ashutosh Litoriya Sriram Kailasam School of Computing and Elect. Engg. Indian Institute of Technology Mandi India Dept. of Computer Sci. and Engg. and IT Jaypee University of Info. Tech. Solan India Genpact India Pvt. Ltd. Bangalore India Dept. of Computer Sci. and Engg. National Institute of Technology Warangal India

ISBN: (数字)9798331509118

ISBN: (纸本)9798331509125

In this digital era, vast amounts of data are generated from various applications, necessitating robust data mining algorithms to extract valuable insights. Subgroup discovery (SD) [1] is a widely used supervised descriptive data mining method that aims to find interesting subgroups of individuals (samples, objects) with high associations to a target property of interest. However, SD faces two major challenges. The first is the high computational expense of exploring the combinatorial search space of subgroups. Second, when testing multiple subgroups to identify a few significant associations, ensuring that each subgroup meets a quality threshold is not enough to control the occurrence of false positives. The latter issue has been addressed recently with permutation testing while for the former, exploring the search space of closed subgroups instead of all possible subgroups reduces the search space without loss of information. Pellegrina et al. [2] incorporated both these approaches and provided a sequential implementation TopKWY for discovering the top-k significant subgroups while controlling false discoveries. It is considered state-of-the-art. However, its huge computational requirement of assessing patterns against many permutations raises scalability concerns, while the specific optimizations in its algorithm for computing p-values do not generalize to other quality functions. Jyoti et al. [3] addressed both these concerns in their proposed framework ParaDiS . The algorithm of ParaDiS is parallel and distributed, employs efficient communication mechanisms for load sharing and generalizes to other quality functions. However, ParaDiS uses exhaustive search and therefore, suffers from performance bottlenecks. The existing heuristic techniques in SD neither control false discoveries nor consider the search space of closed subgroups. Further, these heuristics can miss potentially interesting subgroups w.r.t. quality.

关键词： Scalability High performance computing conferences Aerospace electronics Space exploration Data mining Optimization Faces Testing

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