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检索条件"任意字段=International Conference on Parallel and Distributed Processing Techniques and Applications"

共 11287 条记录，以下是21-30 订阅

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MARO: Enabling Full MPI Automatic Refactoring in DSL-Based Programming Framework 24th

MARO: Enabling Full MPI Automatic Refactoring in DSL-Based ...

引用

24th international conference on Algorithms and Architectures for parallel processing, ICA3PP 2024

作者： Lei, Tong Chen, Zongjing Che, Yonggang Xu, Chuanfu Laboratory of Digitizing Software for Frontier Equipment National University of Defense Technology Changsha410073 China National Key Laboratory of Parallel and Distributed Computing College of Computer Science and Technology National University of Defense Technology Changsha410073 China

ISBN: (纸本)9789819615445

Currently, the landscape of computer hardware architecture presents the characteristics of heterogeneity and diversity, prompting widespread attention to cross-platform portable parallel programming techniques. Most existing portable programming approaches adopt the "MPI+X" strategy, focusing mainly on node-level "X" parallelism, while inter-node parallelization still relies on manual MPI programming. OP2 is a domain-specific language-based portable parallel programming framework for unstructured mesh applications that supports the automatic generation of MPI parallel code. However, programmers must manually write pre-processing code during code refactoring, such as handling the mapping relationship between global and process-local variables and the initial distribution of process-local data. In this paper, we propose MARO (MPI Automatic Refactoring for OP2), an automatic refactoring method for generating pre-processing code targeting MPI code generation within the OP2 programming framework for unstructured mesh applications. This method automatically generates the pre-processing code required for MPI parallelism through the source-to-source translator, enabling OP2 to generate MPI parallel code without requiring users to write MPI-related code manually. We compare the automatically refactored OP2 applications using the proposed method with those manually refactored to validate its effectiveness. The proposed method enhances OP2’s automatic parallel code generation capability, enabling it to achieve fully automatic MPI parallelization. © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2025.

关键词： Automatic programming

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HPC master design: experience from Pisa

HPC master design: experience from Pisa

引用

Euromicro conference on parallel, distributed and Network-Based processing

作者： Marco Danelutto Dept. of Computer Science Univ. of Pisa

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524944

HPC is a widely used term, often referred to the applications, architectures and programming models and tools targeting highly parallel machines such as those of the *** lists. Recent advances in computing hardware resources require application of HPC techniques when using much smaller machines. Indeed, proper parallel programming tools and applications are needed also to exploit parallel hardware resources in personal computers (laptops, desktops, servers). This paper outlines key challenges in designing master’s degree programs in HPC and shares lessons learned from various experiences in developing and implementing such programs in Italy and Europe.

关键词： Portable computers parallel programming High performance computing Europe parallel machines Hardware Telecommunications Stakeholders Servers Programming profession

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Enhancing 6G Network Performance by Reducing Signaling Load via distributed Open RAN and SDN 4

Enhancing 6G Network Performance by Reducing Signaling Load ...

引用

4th international conference on Robotics, Electrical and Signal processing techniques, ICREST 2025

作者： Aldaeabool, Sally. R. Al-Zubaedi, Wesam H. Abbod, M.F. Al-Raweshidy, H.S. Brunel University London Dep. of Electronic and Computer Engineering United Kingdom University of Kerbala Collage of Engineering Dep. of Biomedical Engineering Iraq

ISBN: (纸本)9798331530938

The exponential expansion of mobile communication traffic, fuelled by a rising number of smart devices and sophisticated applications, has put significant pressure on existing cellular network architectures. The 6G networks need creative ways to meet these difficulties effectively. This study offers a distributed Open Radio Access Network (DO-RAN) architecture that uses Open-RAN and Software-Defined Networking (SDN) to reduce signalling burden and boost network performance. DO-RAN improves responsiveness, reduces signalling load on the 5GC, and reduces backhaul congestion by decentralising key functionalities such as the Access and Mobility Management Function (AMF) and the Session Management Function (SMF) from the 5G Core Network (5GC) to the Open-RAN framework's Central Units (CUs). Our proposal compares DO-RAN to Central Open RAN (CO-RAN) and other architectures, such as 4G LTE networks. The findings show that DO-RAN considerably reduces signalling load in a variety of situations, such as network- and user-triggered service events. This architecture provides enhanced efficiency and scalability for 6G cellular networks in addition to meeting the growing demands for signalling. © 2025 IEEE.

关键词： Radio access networks

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A Topological Evaluation Model for Manifold Learning and Embedding techniques 17th

A Topological Evaluation Model for Manifold Learning and Emb...

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17th international conference on Similarity Search and applications

作者： Reyes, Victor Liarou, Margarita Marchand-Maillet, Stephane Univ Geneva Viper Grp Geneva Switzerland

ISBN: (纸本)9783031758225;9783031758232

Data arising from sensors is generally high-dimensional and manifold learning or, more generally, embedding techniques are applied for dimension reduction, possibly with the hope of circumventing the curse of dimensionality. Low-dimensional data may then be the basis for further processing, such as clustering or learning. It is therefore critical that the reduced data representation is faithful to the information contained in the original data. Manifold learning methods are generally evaluated either by visual inspection or by quantifying globally the preservation of neighborhood structures over known dataset. In this paper, we argue for measures that behave smoothly along increasing unfaithfulness to the original data. To build such measures, we return to the manifold assumption and exploit topological information. We further and principally argue for the utility of local measurements of unfaithfulness of representation, as distortions may not be distributed uniformly over the data. The aim here is less to compare manifold techniques than to assess a given technique for its faithfulness. Experiments demonstrate the value of our proposals.

关键词： Evaluation measure Dimension reduction Information embedding Manifold learning Local scale estimation

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Performance Evaluation of NLP Models for European Portuguese: Multi-GPU/Multi-node Configurations and Optimization techniques 24th

Performance Evaluation of NLP Models for European Portugue...

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24th international conference on Algorithms and Architectures for parallel processing, ICA3PP 2024

作者： Santos, Daniel Miquelina, Nuno Schmidt, Daniela Quaresma, Paulo Nogueira, Vítor Beires VISTA Lab ALGORITMI Research Center University of Évora Évora Portugal

ISBN: (纸本)9789819615506

Natural Language processing (NLP) research has predominantly focused on the English language, leading to a wealth of resources and advancements tailored to English. However, there is a growing need to extend these capabilities to other languages, such as European Portuguese, to ensure the inclusivity and accessibility of NLP technologies. In this study, we explore the evaluation of NLP models in the European Portuguese language using a multi-GPU/multi-node machine. We utilized various tools such as PyTorch, Accelerate, Transformers, and DeepSpeed with ZeRO Stage 3 to handle the computational demands of large-scale model training. We provide all the key aspects of our methodology to evaluate various models on translated GLUE tasks. Additionally, we introduce AiBERTa, a base model with 110 million parameters, developed and pre-trained on a corpus tailored for European Portuguese. This research highlights the effectiveness of advanced tools and distributed computing in scaling NLP model training, providing a foundation for future enhancements in European Portuguese language processing. © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2025.

关键词： distributed computer systems

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Developing Scalable and Fault Tolerant distributed Architecture for Big Unstructured Data Systems 6

Developing Scalable and Fault Tolerant Distributed Architect...

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6th international conference on Mobile Computing and Sustainable Informatics, ICMCSI 2025

作者： Saranya, G. Kumaran, K. Pratheep, V. Dhanush, S.R. School of Computer Science and Engineering Vellore Institue of Technology Chennai India

ISBN: (数字)9798331522667

ISBN: (纸本)9798331522667

In the era of big data, efficiently processing and retrieving insights from unstructured data presents a critical challenge. This paper introduces a scalable leader-worker distributed data pipeline designed to handle large sets of unstructured data blobs. Leveraging data parallelism, the system distributes workload across worker nodes, ensuring high performance for embarrassingly parallel tasks with minimal inter-process communication. Fault tolerance is achieved through an optimized next-in-line leader re-election strategy, addressing cascading failures and mitigating the thundering herd effect. The use of Apache Zookeeper for service discovery ensures seamless coordination within the cluster while maintaining a loosely coupled architecture for enhanced scalability. Google Protocol Buffers are employed for secure data transmission, offering tamper resistance against eavesdropping and man-in-the-middle attacks. The system also integrates the TF-IDF algorithm for efficient information retrieval, demonstrating the ability to achieve data parallelism while preserving task uniformity across nodes. Performance evaluation highlights significant reductions in response times with increasing cluster size, validating the system’s scalability, efficiency, and robustness. The proposed architecture is well-suited for real-world applications requiring secure, fault-tolerant, and scalable solutions for unstructured data analysis. © 2025 IEEE.

关键词： Big data

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Etudes for parallel Programmers

Etudes for Parallel Programmers

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Euromicro conference on parallel, distributed and Network-Based processing

作者： Moreno Marzolla Dept of Computer Science and Engineering (DISI) and Center for Inter-Department Industrial Research ICT University of Bologna Bologna Italy

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524944

Mini-applications are widely used in parallel computing for testing and benchmarking purposes. However, many existing mini-applications are not suitable for teaching, since they require advanced knowledge of algebra, numerical analysis or physics to be fully understood, which might be beyond the reach of beginners. In this paper we describe a set of programming assignments, called parallel etudes, that have been used in the last years for teaching High Performance Computing at the undergraduate level. These applications are self-contained, self-documenting, and short. They are drawn from more familiar domains such as 3D rendering, simulation, image processing and simple physics models, to be more accessible to students without a strong mathematical background. The mini-applications target shared-memory, distributed-memory and GPU programming. The analysis of the students’ feedback and final grades provides indirect support for the effectiveness of the etudes.

关键词： Solid modeling Three-dimensional displays parallel programming Source coding High performance computing Education Graphics processing units parallel processing Programming profession Physics

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distributed Branching Random Walks and Their applications 28

Distributed Branching Random Walks and Their Applications

引用

28th international conference on Principles of distributed Systems, OPODIS 2024

作者： Aradhya, Vijeth Gilbert, Seth Götte, Thorsten National University of Singapore Singapore University of Hamburg Germany

ISBN: (纸本)9783959773607

In recent years, the explosion of big data and analytics has necessitated distributed storage and processing with several compute nodes (e.g., multiple datacenters). These nodes collaboratively perform parallel computation, where the data is typically partitioned across these nodes to ensure scalability, redundancy and load-balancing. But the nodes may not always be co-located;in many cases, they are part of a larger communication network. Since those nodes only need to communicate among themselves, a key challenge is to design efficient routes catered to that subnetwork. In this work, we initiate the study of distributed sampling and routing problems for subnetworks in any well-connected network. Given any network G = (V,E) with mixing time τmix, consider the canonical problem of permutation routing [Ghaffari, Kuhn and Su, PODC 2017] that aims to minimize both congestion and dilation of the routes, where the demands (i.e., set of source-terminal pairs) are such that each node sends or receives number of messages proportional to its degree. We show that the permutation routing problem, when demands are restricted to any subset S ⊆ V (i.e., subnetwork), can be solved in exp(O(√log |S|)) · Õ(τmix) rounds (where Õ (·) hides polylogarithmic factors of |V |). This means that the running time depends subpolynomially on the subnetwork size (i.e., not on the entire network size). The ability to solve permutation routing efficiently immediately implies that a large class of parallel algorithms can be simulated efficiently on the subnetwork. As a prerequisite to constructing efficient routes, we design and analyze distributed branching random walks that distribute tokens started by the nodes in the subnetwork. At a high-level, these algorithms operate by always moving each token according to a (lazy) simple random walk, but also branching a token into multiple tokens at some specified intervals;ultimately, if a node starts a branching walk, with its id in a token, then by the

关键词： Graph algorithms

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Efficient Signal processing: Harnessing distributed Arithmetic for High-Speed FFT Operations 3

Efficient Signal Processing: Harnessing Distributed Arithmet...

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3rd international conference on Intelligent and Innovative Technologies in Computing, Electrical and Electronics, IITCEE 2025

作者： Bharathi, M. Mohanarangam, Krithikaa Shirur, Yasha Jyothi M. Andhra Pradesh Tirupati India Symbiosis Institute of Technology Pune India Bnm Institute of Technology Electronics and Communication Engineering Bangalore India

ISBN: (纸本)9798331515911

The present article introduces a novel approach to significantly enhance the computational efficiency of modern Digital Signal processing (DSP) processors. The algorithm enhances the efficiency of Sum of Products (SOP) operations, which are essential for real-time signal processing applications, by utilizing distributed Arithmetic (DA) techniques for the Fast Fourier Transform (FFT) and its inverse (Inverse FFT) (IDFT) computations. The present study undertakes an exhaustive quantitative analysis to assess the computational delays of the proposed 2, 4, and 8-point Fast Fourier Transform (FFT) and Inverse Discrete Fourier Transform (IDFT) across various bit representations (4, 8, and 16-bit). For example, when using 4-bit representations, the computational delays for a 2-point Fast Fourier Transform (FFT) are measured to be 13.318ns, 30.629ns for a 4-point FFT, and 27.779ns for an 8-point FFT. Similarly, the delays for the 2-point Fast Fourier Transform (FFT) in an 8-bit representation are 13.727ns, the 4-point FFT in 22.276ns, and the 8-point FFT in 30.592ns. The study further includes the addition of appropriate delays for IDFT operations, which enhances the understanding of the effectiveness of the approach suggested in various scenarios. Furthermore, the research presents and evaluates three distinct categories of transforms, namely 2-point, 4-point, and 8-point FFT and IDFT structures. These structures utilize different quantities of Look-Up Tables (LUTs) for computational purposes. The research showcases the exceptional computing efficiency of the suggested design through detailed quantitative analysis, emphasizing its potential advantages in improving DSP implementations in practical situations. © 2025 IEEE.

关键词： Inverse problems

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A Performance Model of In-Situ techniques

A Performance Model of In-Situ Techniques

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Euromicro conference on parallel, distributed and Network-Based processing

作者： Yi Ju Nicolas Vidal Adalberto Perez Ana Gainaru Fred Suter Stefano Markidis Philipp Schlatter Scott Klaskyll Erwin Laure Max Planck Computing and Data Facility Oak Ridge National Laboratory Friedrich-Alexander-Universität Erlangen-Nürnberg KTH Royal Institute of Technology

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524944

The computational capacity of High-Performance Computing (HPC) systems increases continuously with the rapid development of central processing units (CPUs) and graphic processing units (GPUs), while the in-/output (IO) subsystem develops relatively slowly and storage capacity is also limited. Data-intensive applications, which are designed to leverage the high computational capacity of HPC resources, typically generate a considerable amount of data for post-processing visualizations and data analytics. The limited IO speed and storage space could lead to constraints in the actual performance of these applications and, therefore, scientific discovery. In-situ techniques, where data is visualized/analysed while still in memory rather than through disk, can contribute to alleviating these problems as they can reduce or even fully avoid data writing/reading through the IO subsystem to/from storage. However, the overall efficiency of insitu techniques crucially depends on the characteristics of both the in-situ tasks and the applications, and the resource distribution among them. Therefore, choosing the right in-situ approach (synchronous, asynchronous, or hybrid) and resource allocation is essential to minimize overhead and maximize the benefits of concurrent execution. In this paper, we present a performance model of in-situ techniques to find the most beneficial in-situ approach and the preferred resource configuration. We verify the high accuracy of our approach with over 6800 measurements and provide use cases with different applications.

关键词： Lead acid batteries Data analysis Accuracy High performance computing Graphics processing units Data visualization Central processing Unit Resource management

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