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Test Oracles Based on Metamorphic Relations for Image processing applications 16

Test Oracles Based on Metamorphic Relations for Image Proces...

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16th IEEE/ACIS international conference on Software Engineering, Artificial Intelligence, Networking and parallel/distributed Computing (SNPD)

作者： Jameel, Tahir Lin, Mengxiang Chao, Liu Beihang Univ State Key Lab Software Dev Environm Beijing Peoples R China Beihang Univ Inst Software Engn Beijing Peoples R China

ISBN: (纸本)9781479986767

Testing of image processing applications is a challenging job especially, when evaluating the correctness of output image. Generally, output images are evaluated manually by visual inspection carried out by an expert tester, which is the main hindrance in automation of testing process. Recently, statistical and metamorphic testing approaches are presented to automate output evaluation of image processing applications. The statistical method is dependent on availability of statistical distribution of output images, whereas metamorphic testing require more research efforts to make it widely used in practice. Metamorphic testing is a well-known technique to alleviate the test oracle problem and eliminates the required manual efforts by using relations of input and output images. Follow-up test cases are generated based on these relations and their expected output is evaluated. This paper addresses test oracle problem for image processing applications and demonstrates how properties of implementation under test can be adopted as metamorphic relations. We have studied general and specific metamorphic relations of morphological image operations such as dilation and erosion. Selection of metamorphic relations and their effectiveness by mutation analysis is demonstrated. The results show that metamorphic testing is useful for evaluation of output images in the absence of a perfect test oracle.

关键词： Testing Imaging applications Metamorphic Testing Test Oracle

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Automatic distributed Code Generation from Formal Models of Asynchronous Concurrent Processes 23

Automatic Distributed Code Generation from Formal Models of ...

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23rd Euromicro international conference on parallel, distributed, and Network-Based processing (PDP)

作者： Evrard, Hugues Lang, Frederic Univ Grenoble Alpes LIG Inria F-38000 Grenoble France CNRS LIG F-38000 Grenoble France

ISBN: (纸本)9781479984909

Formal process languages inheriting the concurrency and communication features of process algebras are convenient formalisms to model distributed applications, especially when they are equipped with formal verification tools (e.g., model-checkers) to help hunting for bugs early in the development process. However, even starting from a fully verified formal model, bugs are likely to be introduced while translating (generally by hand) the concurrent model-which relies on high-level and expressive communication primitives-into the distributed implementation-which often relies on low-level communication primitives. In this paper, we present DLC, a compiler that enables distributed code to be generated from models written in a formal process language called LNT, which is equipped with a rich verification toolbox named CADP. The generated code can be either executed in an autonomous way (i.e., without requiring additional code to be defined by the user), or connected to external software through user-modifiable C functions. We present an experiment where DLC generates a distributed implementation from the LNT model of the Raft consensus algorithm.

关键词： Distribute process algebra concurrent process Communication Research Code generation Formal verification PROCESS DEVELOPMENT bugs Bugs Codes Hunting Language processing distributed coding discotic liquid crystals Asynchronous

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Practical Near-Data processing for In-memory Analytics Frameworks 24

Practical Near-Data Processing for In-memory Analytics Frame...

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24th international conference on parallel Architecture and Compilation (PACT)

作者： Gao, Mingyu Ayers, Grant Kozyrakis, Christos Stanford Univ Stanford CA 94305 USA

ISBN: (纸本)9781467395243

The end of Dennard scaling has made all systems energy-constrained. For data-intensive applications with limited temporal locality, the major energy bottleneck is data movement between processor chips and main memory modules. For such workloads, the best way to optimize energy is to place processing near the data in main memory. Advances in 3D integration provide an opportunity to implement near-data processing (NDP) without the technology problems that similar efforts had in the past. This paper develops the hardware and software of an NDP architecture for in-memory analytics frameworks, including MapReduce, graph processing, and deep neural networks. We develop simple but scalable hardware support for coherence, communication, and synchronization, and a runtime system that is sufficient to support analytics frameworks with complex data patterns while hiding all the details of the NDP hardware. Our NDP architecture provides up to 16x performance and energy advantage over conventional approaches, and 2.5x over recently-proposed NDP systems. We also investigate the balance between processing and memory throughput, as well as the scalability and physical and logical organization of the memory system. Finally, we show that it is critical to optimize software frameworks for spatial locality as it leads to 2.9x efficiency improvements for NDP.

关键词： Near-data processing processing in memory Energy efficiency In-memory analytics

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A Hybrid Scheduling Algorithm based on Self-Timed and Periodic Scheduling for Embedded Streaming applications 23

A Hybrid Scheduling Algorithm based on Self-Timed and Period...

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23rd Euromicro international conference on parallel, distributed, and Network-Based processing (PDP)

作者： Dkhil, Amira Xuan Khanh Do Louise, Stephane Rochange, Christine CEA LIST PC172 F-91191 Gif Sur Yvette France Univ Toulouse IRIT Toulouse France

ISBN: (纸本)9781479984909

In this paper, we consider the problem of multiprocessor scheduling for safety-critical streaming applications modeled as acyclic data-flow graphs. To the best of our knowledge, most existing works have proposed periodic scheduling that ignore latency or can even have a negative impact on it: the results are quite far from those obtained under Self-Timed scheduling (STS). In this paper, we introduce a new scheduling policy noted Self-Timed Periodic (STP), which is an execution model combining self-timed scheduling with periodic scheduling. The proposed framework shows that the use of both strategies is possible and that they complement each other;STS improves the performance metrics of the programs, while the periodic model captures the timing aspects. We evaluate the performance of our scheduling policy for a set of 10 real-life streaming applications. We find that in most of the cases, our approach gives a significant improvement in latency compared to the Static Periodic Schedule (SPS), and results which are close to the best case latency of STS.

关键词： Latency Real-time multiprocessor scheduling Streaming applications Latency scheduling policy Periodic space transport system STS gene Performance metrics Streaming scheduling of multiprocessor

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Monitoring Traffic in Computer Networks with Dynamic distributed Remote Packet Capturing

Monitoring Traffic in Computer Networks with Dynamic Distrib...

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IEEE international conference on Communications (ICC)

作者： Gad, Ruediger Kappes, Martin Medina-Bulo, Inmaculada Frankfurt Univ Appl Sci Frankfurt Germany Univ Cadiz Cadiz Spain

ISBN: (纸本)9781467364324

We present an approach for flexible distributed remote packet capturing with additional self-adaptivity and cooperation capabilities. Such techniques are needed for gaining comprehensive insight into large computer networks. With our system it is possible to operate multiple distributed remote packet capturing sensors from arbitrary locations. Advanced features like self-adaptivity or the cooperative use of sensors help to increase the performance. Empirical results obtained with a prototype indicate that our approach is efficient and allows capturing of traffic with speeds in the order of magnitude of Gigabit Ethernet. Furthermore, our approach integrates with and enables the use of existing packet processing applications.

关键词： Packet Capturing distributed Remote

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Integrating query processing with parallel languages 31

Integrating query processing with parallel languages

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2015 31st IEEE international conference on Data Engineering Workshops, ICDEW 2015

作者： Myers, Brandon University of Washington United States

ISBN: (纸本)9781479984411

In this thesis we propose new techniques for using parallel languages to improve query processing. Optimizing a query plan and its particular implementation is important for efficient processing on modern systems. First, we present our work on a parallel representation of queries using partitioned global address space languages that enables new optimizations. Next, we propose future work on cooperative optimization of query plans and imperative programs in the context of parallel applications that include queries. © 2015 IEEE.

关键词： Query processing

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Compiler Assisted Load Balancing on Large Clusters 24

Compiler Assisted Load Balancing on Large Clusters

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24th international conference on parallel Architecture and Compilation (PACT)

作者： Deodhar, Vinit Parikh, Hrushit Gavrilovska, Ada Pande, Santosh Georgia Inst Technol Coll Comp Atlanta GA 30332 USA Georgia Inst Technol Sch Elect & Comp Engn Atlanta GA 30332 USA

ISBN: (纸本)9781467395243

Load balancing of tasks across processing nodes is critical for achieving speed up on large scale clusters. Load balancing schemes typically detect the imbalance and then migrate the load from an overloaded processing node to an idle or lightly loaded processing node and thus, estimation of load critically affects the performance of load balancing schemes. On large scale clusters, the latency of load migration between processing nodes (and the energy) is also a significant overhead and any missteps in load estimation can cause significant migrations and performance losses. Currently, the load estimation is done either by profile or feedback driven approaches in sophisticated systems such as Charm++, but such approaches must be re-thought in light of some workloads such as Adaptive Mesh Refinement (AMR) and multiscale physics where the load variations could be quite dynamic and rapid. In this work we propose a compiler based framework which performs precise prediction of the forthcoming workload. The compiler driven load prediction technique performs static analysis of a task and derives an expression to predict load of a task and hoists it as early as possible in the control flow of execution. The compiler also inserts corrector expressions at strategic program points which refine the reachability probability of the load as well as its estimation. The predictor and the corrector expressions are evaluated at runtime and the predicted load information is refined as the execution proceeds and is eventually used by load balancer to take efficient migration decisions. We present an implementation of the above in the Rose compiler and the Charm++ parallel programming framework. We demonstrate the effectiveness of the framework on some key benchmarks that exhibit dynamic variations and show how the compiler framework assists load balancing schemes in Charm++ to provide significant gains.

关键词： distributed computing Processor scheduling parallel programming Petascale Computing

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Scalable SIMD-Efficient Graph processing on GPUs 24

Scalable SIMD-Efficient Graph Processing on GPUs

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24th international conference on parallel Architecture and Compilation (PACT)

作者： Khorasani, Farzad Gupta, Rajiv Bhuyan, Laxmi N. Univ Calif Riverside Dept Comp Sci & Engn Riverside CA 92521 USA

ISBN: (纸本)9781467395243

The vast computing power of GPUs makes them an attractive platform for accelerating large scale data parallel computations such as popular graph processing applications. However, the inherent irregularity and large sizes of real-world power law graphs makes effective use of GPUs a major challenge. In this paper we develop techniques that greatly enhance the performance and scalability of vertex-centric graph processing on GPUs. First, we present Warp Segmentation, a novel method that greatly enhances GPU device utilization by dynamically assigning appropriate number of SIMD threads to process a vertex with irregular-sized neighbors while employing compact CSR representation to maximize the graph size that can be kept inside the GPU global memory. Prior works can either maximize graph sizes (VWC [11] uses the CSR representation) or device utilization (e.g., CuSha [13] uses the CW representation;however, CW is roughly 2.5x the size of CSR). Second, we further scale graph processing to make use of multiple GPUs while proposing Vertex Refinement to address the challenge of judiciously using the limited bandwidth available for transferring data between GPUs via the PCIe bus. Vertex refinement employs parallel binary prefix sum to dynamically collect only the updated boundary vertices inside GPUs' outbox buffers for dramatically reducing inter-GPU data transfer volume. Whereas existing multi-GPU techniques (Medusa [31], TOTEM [7]) perform high degree of wasteful vertex transfers. On a single GPU, our framework delivers average speedups of 1.29x to 2.80x over VWC. When scaled to multiple GPUs, our framework achieves up to 2.71x performance improvement compared to inter-GPU vertex communication schemes used by other multi-GPU techniques (i.e., Medusa, TOTEM).

关键词： Graphs Power Law Graphs GPU Irregular Computations Scalability Multi-GPU

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Processor-in-memory support for artificial neural networks

Processor-in-memory support for artificial neural networks

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IEEE international conference on Rebooting Computing (ICRC)

作者： Joshua Schabel Lee Baker Sumon Dey Weifu Li Paul D. Franzon Department of Electrical and Computer Engineering North Carolina State University Raleigh North Carolina

ISBN: (纸本)9781509013715

Hardware acceleration of artificial neural network (ANN) processing has potential for supporting applications benefiting from real time and low power operation, such as autonomous vehicles, robotics, recognition and data mining. Most interest in ANNs targets acceleration of deep multi-layered ANNs that can require days of offline training to converge on a desired network behavior. Interest has grown in ANNs capable of supporting unsupervised training, where networks can learn new information from unlabeled data dynamically without the need for offline training. These ANNs require large memories with bandwidths much higher than supported in modern GPGPUs. Custom hardware acceleration and memory co-design holds the potential to provide real-time performance in cases where the performance requirements cannot be met by modern GPGPUs. This work presents a custom processor solution to accelerate two hetero-associative memories (Sparsey and HTM) capable of unsupervised and one-hot learning. This custom processor is implemented as an expandable ASIP built upon a configurable SIMD engine for exploiting parallelism. Functional specialization is implemented utilizing processor-in-memory techniques, which results in up to a 20× speedup and a 2000× reduction in energy per frame compared to a software implementation operating on a dataset for recognition of human actions.

关键词： Acceleration Engines VLIW parallel processing Training Bandwidth Algorithm design and analysis

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Dynamic message processing and transactional memory in the actor model 15

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15th IFIP WG 6.1 international conference on distributed applications and Interoperable Systems, DAIS 2015 Held as Part of the 10th international Federated conference on distributed Computing techniques, DisCoTec 2015

作者： Hayduk, Yaroslav Sobe, Anita Felber, Pascal University of Neuchatel Switzerland

ISBN: (纸本)9783319191287

With the trend of ever growing data centers and scaling core counts, simple programming models for efficient distributed and concurrent programming are required. One of the successful principles for scalable computing is the actor model, which is based on message passing. Actors are objects that hold local state that can only be modified by the exchange of messages. To avoid typical concurrency hazards, each actor processes messages sequentially. However, this limits the scalability of the model. We have shown in former work that concurrent message processing can be implemented with the help of transactional memory, ensuring sequential processing, when required. This approach is advantageous in low contention phases, however, does not scale for high contention phases. In this paper we introduce a combination of dynamic resource allocation and non-transactional message processing to overcome this limitation. This allows for efficient resource utilization as these two mechanisms can be handled in parallel. We show that we can substantially reduce the execution time of high-contention workloads in a micro-benchmark as well as in a real-world application. © IFIP international Federation for Information processing 2015.

关键词： Message passing

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