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15th international conference on Computer Aided Systems Theory, EUROCAST 2015

15th International Conference on Computer Aided Systems Theo...

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15th international conference on Computer Aided Systems Theory, EUROCAST 2015

ISBN: (纸本)9783319273396

The proceedings contain 107 papers. The special focus in this conference is on Systems Theory and applications. The topics include: A simple linearisation of the self-shrinking generator;systems theory and model of diversification in building of information systems;time sub-optimal control of triple integrator applied to real three-tank hydraulic system;use of the automatic identification system in academic research;application of multi-valued decision diagrams in computing the direct partial logic derivatives;identification of first order plants by relay feedback with non-symmetrical oscillations;managing certificate revocation in VANETs using hash trees and query frequencies;constrained pole assignment control for a 2nd order oscillatory system;parallel and distributed metaheuristics;dynamic similarity and distance measures based on quantiles;eulerian numbers weigths in distributed computing nets;autonomous paracopter control design;a class of 3-D distributed modular computing nets;standardized mapping model for heritage preservation and serendipity in cloud;structuring the model of complex system using parallel computing techniques;some remarks on first-passage times for integrated gauss-markov processes;a sequential test for evaluating air quality;population models and enveloping;fractional growth process with two kinds of jumps;towards stochastic modeling of neuronal interspike intervals including a time-varying input signal;a cancer dynamics model for an intermittent treatment involving reduction of tumor size and rise of growth rate;on time non-homogeneous feller-type diffusion process in neuronal modeling and a practical experience on reusing problem-solving methods for assessment tasks.

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HDL Design for 32 Port Real Time Tera Hertz (Tbps) Wi-Fi Router ASIC Soft IP Core for Complex Network-On-Chip wireless Internet & Cloud Computing applications 5

HDL Design for 32 Port Real Time Tera Hertz (Tbps) Wi-Fi Rou...

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2015 Fifth international conference on Communication Systems and Network Technologies (CSNT)

作者： Sastry, P. N. V. M. Rao, D. N. Vathsal, S. JBREC IT EDA Software Ind CELL & R&D CELL & ECE Dept Hyderabad 75 Andhra Pradesh India JBREC Hyderabad 75 Andhra Pradesh India JBIET EEE Dept R&D EEE Hyderabad 75 Andhra Pradesh India

ISBN: (纸本)9781479917976

The Aim is to HDL Design Implementation of 32x32 Port Wi-Fi Router for Complex NOC Computing applications like Internet and cloud computing networks. This router is the main component in Network on Chip, the advantage is very simple and reliable for High Speed parallel distributed Pipe Line Data processing Computing technique and very suit for complex NOC Computing application products 3G, 4G wireless Mobile Computing like Tablets, IPhones, Epads, Notebook Computers. The Importance and Usage of the router is for reduction of number of NOC components and Internet & Cloud traffic networks Complexity and Dataloss. This paper focuses on the Architecture Design and Implementation, Verification of 32 Port Router ASIC Card. The Building Blocks are Buffering Registers, Demultiplexers, FIFOs, and Schedulers. This Router Architecture Simulated by Xilinx ISE 9.2i/Altera Quartus II Software. Code written by using VHDL/Verilog HDL Programming & Debugging Done By Advanced Xilinx /Altera / Cypress FPGA Development Board.

关键词： NOC - Network On Chip VHDL - Very High Speed Integrated Circuit Hardware Description Language ASIC- Application Specific Integrated Circuits FPGA-Field Programmable-Gate-Array FIFO-First In First Out

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A study of pupil detection and tracking by image processing techniques for a human eye-computer interaction system

A study of pupil detection and tracking by image processing ...

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ACIS international conference on Software Engineering, Artificial Intelligence, Networking, and parallel/distributed Computing (SNPD)

作者： Ryo Shimata Yoshihiro Mitani Tsumoru Ochiai Department of Intelligent System and Engineering National Institute of Technology Ube Japan

The pupil detection and tracking is an important step for developing a human-computer interaction system. To develop a human eye-computer interaction system, we examine pupil detection and tracking by image processing techniques. In the image processing techniques, the illumination directly influences the image quality in general. If influences of illumination is little, we can obtain an image of good image quality. The subsequent image processing techniques are expected almost to succeed. In this paper, in order to avoid the influences of illumination, we have tried to combine the hardware constitution of an infrared light-emitting diode (LED) light, a sensitive infrared camera, and an infrared (IR) filter. In the experiment with this hardware constitution, we investigate the effects of the pupil detection and tracking by image processing techniques for a human eye-computer interaction system.

关键词： Image processing Lighting Cameras Hardware Constitution Light emitting diodes Tracking

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6th international conference on Fundamentals of Software Engineering, FSEN 2015

6th International Conference on Fundamentals of Software Eng...

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6th international conference on Fundamentals of Software Engineering, FSEN 2015

ISBN: (纸本)9783319246437

The proceedings contain 21 papers. The special focus in this conference is on Fundamentals of Software Engineering. The topics include: Towards smart systems of systems;automated integration of service-oriented software systems;software architecture modeling and evaluation based on stochastic activity networks;modeling and efficient verification of broadcasting actors;a theory of integrating tamper evidence with stabilization;a safe stopping protocol to enable reliable reconfiguration for component-based distributed systems;efficient architecture-level configuration of large-scale embedded software systems;benchmarks for parity games;incremental realization of safety requirements;analyzing mutable checkpointing via invariants;high performance computing applications using parallel data processing units;improved iterative methods for verifying markov decision processes;a pre-congruence format for xy-simulation;tooled process for early validation of sysML models using modelica simulation;painless support for static and runtime verification of component-based applications;linear evolution of domain architecture in service-oriented software product lines;an interval-based approach to modelling time in event-B and from event-B models to dafny code contracts.

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MatrixMap: Programming Abstraction and Implementation of Matrix Computation for Big Data applications

MatrixMap: Programming Abstraction and Implementation of Mat...

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international conference on parallel and distributed Systems (ICPADS)

作者： Yaguang Huangfu Jiannong Cao Hongliang Lu Guanqing Liang Department of Computing The Hong Kong Polytechnic University Parallel and Distributed Processing Laboratory National University of Defense Technology

The computation core of many big data applications can be expressed as general matrix computations, including linear algebra operations and irregular matrix operations. However, existing parallel programming systems such as Spark do not have programming abstraction and efficient implementation for general matrix computations. In this paper, we present MatrixMap, a unified and efficient data-parallel system for general matrix computations. MatrixMap provides powerful yet simple abstraction, consisting of a distributed data structure called bulk key matrix and a computation interface defined by matrix patterns. Users can easily load data into bulk key matrices and program algorithms into parallel matrix patterns. MatrixMap outperforms current state-of-the-art systems by employing three key techniques: matrix patterns with lambda functions for irregular and linear algebra matrix operations, asynchronous computation pipeline with optimized data shuffling strategies for specific matrix patterns and in-memory data structure reusing data in iterations. Moreover, it can automatically handle the parallelization and distribute execution of programs on a large cluster. The experiment results show that MatrixMap is 12 times faster than Spark.

关键词： Data structures Programming Linear algebra Machine learning algorithms Sparks Sparse matrices Computational modeling

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2015 4th international conference on Software Engineering and Computer Systems, ICSECS 2015: Virtuous Software Solutions for Big Data

2015 4th International Conference on Software Engineering an...

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4th international conference on Software Engineering and Computer Systems, ICSECS 2015

ISBN: (纸本)9781467367226

The proceedings contain 40 papers. The topics discussed include: hybrid storage architecture for video on demand server;performance of various speckle reduction filters on synthetic aperture radar image;state of mobile crowdsourcing applications: a review;performance evaluation of completed local ternary patterns (CLTP) for medical, scene and event image categorization;a literature review on gold price predictive techniques;a review on parallel medical image processing on GPU;collaborative knowledge management system strategic planning (CKMS2P): a systematic literature review;big data maturity model for Malaysian Zakat institutions to embark on big data initiatives;automated secure room system;evacuation plan based on tsunami alert simulator;and linear model predictive control of a debutanizer column.

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Holistic Management of Sustainable Geo-distributed Data Centers 22

Holistic Management of Sustainable Geo-Distributed Data Cent...

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22nd international conference on High Performance Computing

作者： Abbasi, Zahra Gupta, Sandeep K. S. Ericsson Res San Jose CA USA Arizona St Univ IMPACT Lab Tempe AZ USA

ISBN: (纸本)9781467384889

This paper designs a holistic global workload management solution which explores diversities of a set of geo-distributed data centers and energy buffering in order to minimize the electricity cost, reduce the peak power drawn from utilities while maintaining the carbon capping requirement of the data centers. The prior work often designed solutions to address each of the aforementioned energy and cost optimization separately, disregarding the possible conflicts between the solutions' objectives. We propose a holistic solution to concurrently optimize the aforementioned potentially competing objectives. The proposed solution combines the techniques from Lyapunov optimization and predictive solution in order to manage the tradeoffs of electricity cost and carbon footprint reduction, and electricity cost and peak power cost reduction, respectively. The predicted data center parameters, being a significant aid to near optimally manage energy buffering and smoothing data centers' peak power draw, adversely affect the peak power cost due to the parameters' prediction error. The proposed holistic solution adapts stochastic programing to take the predicted parameters' randomness into consideration for minimizing the harmful impact of the prediction error. Our trace -based study confirms our analytical result that our holistic solution balances all the tradeoffs towards achieving energy and cost sustainability. Also our solution removes up to 66% of the prediction error impact in increasing the cost.

关键词： data centers cloud computing peak power prediction error carbon capping electricity cost

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Runtime-Aware Architectures 21st

Runtime-Aware Architectures

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21st international conference on parallel and distributed Computing (Euro-Par)

作者： Casas, Marc Moreto, Miquel Alvarez, Lluc Castillo, Emilio Chasapis, Dimitrios Hayes, Timothy Jaulmes, Luc Palomar, Oscar Unsal, Osman Cristal, Adrian Ayguade, Eduard Labarta, Jesus Valero, Mateo Univ Politecn Cataluna Barcelona Supercomp Ctr Barcelona Spain

ISBN: (纸本)9783662480960;9783662480953

In the last few years, the traditional ways to keep the increase of hardware performance to the rate predicted by the Moore's Law have vanished. When uni-cores were the norm, hardware design was decoupled from the software stack thanks to a well defined Instruction Set Architecture (ISA). This simple interface allowed developing applications without worrying too much about the underlying hardware, while hardware designers were able to aggressively exploit instruction-level parallelism (ILP) in superscalar processors. Current multi-cores are designed as simple symmetric multiprocessors (SMP) on a chip. However, we believe that this is not enough to overcome all the problems that multi-cores face. The runtime system of the parallel programming model has to drive the design of future multi-cores to overcome the restrictions in terms of power, memory, programmability and resilience that multi-cores have. In the paper, we introduce an approach towards a Runtime-Aware Architecture (RAA), a massively parallel architecture designed from the runtime's perspective.

关键词： parallel architectures

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Graph Coloring on the GPU and Some techniques to Improve Load Imbalance

Graph Coloring on the GPU and Some Techniques to Improve Loa...

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IEEE international Symposium on parallel and distributed processing Workshops and Phd Forum (IPDPSW)

作者： Shuai Che Gregory Rodgers Brad Beckmann Steve Reinhardt AMD Research

ISBN: (纸本)9781467376853

Graphics processing units (GPUs) have been increasingly used to accelerate irregular applications such as graph and sparse-matrix computation. Graph coloring is a key building block for many graph applications. The first step of many graph applications is graph coloring/partitioning to obtain sets of independent vertices for subsequent parallel computations. However, parallelization and optimization of coloring for GPUs have been a challenge for programmers. This paper studies approaches to implementing graph coloring on a GPU and characterizes their program behaviors with different graph structures. We also investigate load imbalance, which can be the main cause for performance bottlenecks. We evaluate the effectiveness of different optimization techniques, including the use of work stealing and the design of a hybrid algorithm. We are able to improve graph coloring performance by approximately 25% compared to a baseline GPU implementation on an AMD Radeon HD 7950 GPU. We also analyze some important factors affecting performance.

关键词： Graphics processing units Instruction sets Color Labeling Arrays Image color analysis Algorithm design and analysis

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A Fast and Scalable Graph Coloring Algorithm for Multi-core and Many-core Architectures 21st

A Fast and Scalable Graph Coloring Algorithm for Multi-core ...

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21st international conference on parallel and distributed Computing (Euro-Par)

作者： Rokos, Georgios Gorman, Gerard Kelly, Paul H. J. Univ London Imperial Coll Sci Technol & Med Dept Comp Software Performance Optimisat Grp London SW7 2AZ England Univ London Imperial Coll Sci Technol & Med Dept Earth Sci & Engn Appl Modelling & Computat Grp London SW7 2AZ England

ISBN: (纸本)9783662480960;9783662480953

Irregular computations on unstructured data are an important class of problems for parallel programming. Graph coloring is often an important preprocessing step, e.g. as a way to perform dependency analysis for safe parallel execution. The total run time of a coloring algorithm adds to the overall parallel overhead of the application whereas the number of colors used determines the amount of exposed parallelism. A fast and scalable coloring algorithm using as few colors as possible is vital for the overall parallel performance and scalability of many irregular applications that depend upon runtime dependency analysis. Catalyurek et al. have proposed a graph coloring algorithm which relies on speculative, local assignment of colors. In this paper we present an improved version which runs even more optimistically with less thread synchronization and reduced number of conflicts compared to Catalyurek et al.'s algorithm. We show that the new technique scales better on multicore and many-core systems and performs up to 1.5x faster than its predecessor on graphs with high-degree vertices, while keeping the number of colors at the same near-optimal levels.

关键词： Graph coloring Greedy coloring First-fit coloring Irregular data parallel graph algorithms Shared-memory parallelism Optimistic execution Many-core architectures Intel (R) Xeon Phi (TM)

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