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A customizable MapReduce framework for complex data-intensive workflows on GPUs

A customizable MapReduce framework for complex data-intensiv...

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IEEE international conference on Performance, Computing and Communications (IPCCC)

作者： Zhi Qiao Shuwen Liang Hai Jiang Song Fu Department of Computer Science and Engineering University of North Texas Department of Computer Science Arkansas State University

The MapReduce programming model has been widely used in big data and cloud applications. Criticism on its inflexibility when being applied to complicated scientific applications recently emerges. Several techniques have been proposed to enhance its flexibility. However, some of them exert special requirements on applications, while others fail to support the increasingly popular coprocessors, such as Graphics processing Unit (GPU). In this paper, we propose MR-Graph, a customizable and unified framework for GPU-based MapReduce, which aims to improve the flexibility and performance of MapReduce. MR-Graph addresses the limitations and restrictions of the traditional MapReduce execution paradigm. The three execution modes integrated in MR-Graph facilitates users to write their applications in a more flexible fashion by defining a Map and Reduce function call graph. MR-Graph efficiently explores the memory hierarchy in GPUs to reduce the data transfer overhead between execution stages and accommodate big data *** have implemented a prototype of MR-Graph and experimental results show the effectiveness of using MR-Graph for flexible and scalable GPU-based MapReduce computing.

关键词： Graphics processing units Programming Computational modeling Data models parallel processing Big data Computer architecture

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AREP: Adaptive Resource Efficient Prefetching for Maximizing Multicore Performance

AREP: Adaptive Resource Efficient Prefetching for Maximizing...

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international conference on parallel Architecture and Compilation techniques (PACT)

作者： Muneeb Khan Michael A. Laurenzanoy Jason Marsy Erik Hagersten David Black-Schaffer Uppsala University and University of Michigan Ann Arbor Uppsala Univ. & Univ. of Michigan Ann Arbor MI USA

Modern processors widely use hardware prefetching to hide memory latency. While aggressive hardware prefetchers can improve performance significantly for some applications, they can limit the overall performance in highly-utilized multicore processors by saturating the offchip bandwidth and wasting last-level cache capacity. Co-executing applications can slowdown due to contention over these shared resources. This work introduces Adaptive Resource Efficient Prefetching (AREP) -- a runtime framework that dynamically combines software prefetching and hardware prefetching to maximize throughput in highly utilized multicore processors. AREP achieves better performance by prefetching data in a resource efficient way -- conserving offchip-bandwidth and last-level cache capacity with accurate prefetching and by applying cache-bypassing when possible. AREP dynamically explores a mix of hardware/software prefetching policies, then selects and applies the best performing policy. AREP is phase-aware and re-explores (at runtime) for the best prefetching policy at phase boundaries. A multitude of experiments with workload mixes and parallel applications on a modern high performance multicore show that AREP can increase throughput by up to 49% (8.1% on average). This is complemented by improved fairness, resulting in average quality of service above 94%.

关键词： Prefetching Hardware Runtime Bandwidth Multicore processing

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A MapReduce Algorithm for Polygon Retrieval in Geospatial Analysis

A MapReduce Algorithm for Polygon Retrieval in Geospatial An...

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IEEE international conference on Cloud Computing

作者： Qiulei Guo Balaji Palanisamy Hassan A. Karimi School of Information Sciences University of Pittsburgh

The proliferation of data acquisition devices like 3D laser scanners had led to the burst of large-scale spatial terrain data which imposes many challenges to spatial data analysis and computation. With the advent of several emerging cloud technologies, a natural and cost-effective approach to managing such large-scale data is to store and process such datasets in a publicly hosted cloud service using modern distributed computing paradigms such as MapReduce. For several key spatial data analysis and computation problems, polygon retrieval is a fundamental operation which is often computed under real-time constraints. However, existing sequential algorithms fail to meet this demand effectively given that terrain data in recent years have witnessed an unprecedented growth in both volume and rate. In this work, we present a MapReduce-based parallel polygon retrieval algorithm which aims at minimizing the IO and CPU loads of the map and reduce tasks during spatial data processing. Our proposed algorithm first hierarchically indexes the spatial terrain data using a quad-tree index, with the help of which, a significant amount of data is filtered out in the pre-processing stage based on the query object. In addition, a prefix tree based on the quad-tree index is built to query the relationship between the terrain data and query area in real time which leads to significant savings in both I/O load and CPU time. The performance of the proposed techniques is evaluated in a Hadoop cluster and the results demonstrate that the proposed techniques are scalable and lead to more than 35% reduction in execution time of the polygon retrieval operation over existing distributed algorithms.

关键词： Tin Indexes Spatial databases distributed databases Real-time systems Computational modeling Partitioning algorithms

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Designing Bit-Reproducible Portable High-Performance applications

Designing Bit-Reproducible Portable High-Performance Applica...

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IEEE 28th international parallel & distributed processing Symposium (IPDPS)

作者： Arteaga, Andrea Fuhrer, Oliver Hoefler, Torsten Swiss Fed Inst Technol Zurich Switzerland Fed Off Meteorol & Climatol MeteoSwiss Zurich Switzerland

ISBN: (纸本)9780769552071

Bit-reproducibility has many advantages in the context of high-performance computing. Besides simplifying and making more accurate the process of debugging and testing the code, it can allow the deployment of applications on heterogeneous systems, maintaining the consistency of the computations. In this work we analyze the basic operations performed by scientific applications and identify the possible sources of non-reproducibility. In particular, we consider the tasks of evaluating transcendental functions and performing reductions using non-associative operators. We present a set of techniques to achieve reproducibility and we propose improvements over existing algorithms to perform reproducible computations in a portable way, at the same time obtaining good performance and accuracy. By applying these techniques to more complex tasks we show that bit-reproducibility can be achieved on a broad range of scientific applications.

关键词： determinism reproducibility parallelism IEEE-754 standard

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Atomic stream computation unit based on micro-thread level parallelism

Atomic stream computation unit based on micro-thread level p...

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international conference on Application Specific Systems (ASAP), Architectures and Processors

作者： Nasim Farahini Ahmed Hemani Electronics and Embedded Systems Group KTH Sweden

The increasing demand for higher resolution of images and communication bandwidth requires the streaming applications to deal with ever increasing size of datasets. Further, with technology scaling the cost of moving data is reducing at a slower pace compared to the cost of computing. These trends have motivated the proposed micro-architectural reorganization of stream processors by dividing the stream computation into functional computation, address constraints computation and address generation and deploying independent, distributed micro-threads to implement them. This scheme is an alternative to parallelizing them at instruction level. The proposed scheme has two benefits: a more efficient sequencer logic and energy savings in address generation and transportation. These benefits are quantified for a set of streaming applications and show average percentage improvement of 39 in silicon efficiency of the sequencer logic and 23 in total computational efficiency.

关键词： Instruction sets Computer architecture Transportation VLIW Memory Streaming media parallel processing

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Implementation of Gaussian and Box Kernel Based Approximation of Bilateral Filter Using OpenCL

Implementation of Gaussian and Box Kernel Based Approximatio...

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Proceedings of the Digital Image Computing: Technqiues and applications (DICTA)

作者： Honey Gupta Daniel Sanju Antony G. N. Rathna Visvesvaraya National Institute of Technology Nagpur India Indian Institute of Science Bangalore India Indian Institute of Science Bangalore Karnataka IN

A Bilateral filter is basically an edge-preserving and smoothing, non-linear filter. It consists of two kernels, namely spatial and range kernels which can be constant or arbitrary. Algorithms for bilateral filtering with constant time computational complexity are present today, but their execution time is too high for real time applications. Also, hardware latency and throughput sometimes reduce the speed of filtering. In this paper, we introduce a novel algorithm for bilateral filtering in which we combine box spatial kernel with Gauss-Polynomial range kernel. parallel implementation of the algorithm is done on GPU (AMD Radeon HD 7650M) using OpenCL and an average run time of 15ms is achieved for an image of dimensions 256 x 256. Results of this algorithm is found to be about 15 times faster than the parallel implementation of bilateral filter with Gaussian spatial kernel and Gauss-Polynomial range kernel. We infer that while the PSNR values obtained are very close, there is a significant improvement in run-time when we use the proposed algorithm.

关键词： Kernel Filtering algorithms Graphics processing units Filtering Convolution Hardware Standards

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GPU Accelerated Background Subtraction

GPU Accelerated Background Subtraction

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2015 IEEE 16th international conference on Communication Technology(ICCT 2015)

作者： Dan Liu Science and Technology on Communication Security Laboratory

Background subtraction is a crucial step in many automatic video content analysis applications. While numerous acceptable techniques have been proposed so far for background extraction, there is still a need to produce more efficient algorithms in terms of computation efficiency. Some complex algorithms usually give better results, but are too slow to be applied to real-time systems. This paper describes ViBe algorithm for background subtraction and presents implementation of it using the CUDA technology for parallel processing. The experiments indicate that our implementation outperforms the majority of earlier state-of-the-art algorithms not only in terms of accuracy, but also in terms of processing speed.

关键词： Background subtraction CUDA parallel computing Computer vision GPU

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Towards Optimal Task Distribution on Computer Clusters with Intel MIC Coprocessors

Towards Optimal Task Distribution on Computer Clusters with ...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Chenggang Lai Miaoqing Huang Genlang Chen Department of Computer Science and Computer Engineering University of Arkansas Ningbo Institute of Technology Zhejiang University

ISBN: (纸本)9781479989386

Computer clusters with coprocessors/accelerators are typically leveraged to parallelize applications for reducing computation time. Given N parallel tasks and M processing cores, the typical strategy is to statically distribute those N tasks among M cores so that each core receives N/M tasks. However, for many sophisticated applications, the processing times of N tasks may vary. In other words, some tasks will take longer time than others. The static distribution will cause the cores with light tasks to wait for the cores with the heavy tasks, resulting in an imbalance in task distribution and the nonminimal overall processing time for the application. In this work we apply dynamic task distribution. All the unfinished tasks form a task pool. Once a core finishes a task, it will request a new task from the task pool. Through this manner, all cores will be kept busy in the whole computation process. We apply two additional optimization techniques to further improve the performance of applications on clusters with Intel MIC coprocessors. First, we design hybrid implementations to distribute tasks to both the CPUs and MICs. Second, we apply multiple-level parallelism technique to realize the concurrency among the N tasks as well as the concurrency in each task. We use sparse coding as a case study to demonstrate the advantages of our approach. Sparse coding is a class of unsupervised methods for learning sets of over-complete bases to represent data efficiently. The aim of sparse coding is to find a set of basis vectors such that an input vector can be represented as a linear combination of these basis vectors. The results show that the dynamic task distribution can improve the performance by 25% compared with the static one. Further, the hybrid mode implementation involving both the host CPUs and the MICs can outperform the basic offload mode implementation by 40%.

关键词： Microwave integrated circuits parallel processing Encoding Coprocessors Dictionaries Instruction sets Computers

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Vector parallelism in JavaScript: Language and Compiler Support for SIMD

Vector Parallelism in JavaScript: Language and Compiler Supp...

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international conference on parallel Architecture and Compilation techniques (PACT)

作者： Ivan Jibaja Peter Jensen Ningxin Hu Mohammad R. Haghighat John McCutchan Dan Gohman Stephen M. Blackburn Kathryn S. McKinley University of Texas at Austin Austin TX US Intel Corporation Google Inc. Mozilla Australian National University Microsoft Research

JavaScript is the most widely used web programming language and is increasingly used to implement sophisticated and demanding applications in such domains as graphics, games, video, and cryptography. The performance and energy usage of these applications can benefit from hardware parallelism, including SIMD (Single Instruction, Multiple Data) vector parallel instructions. JavaScript's current support for parallelism is, however, limited and does not directly utilize SIMD capabilities. This paper presents the design and implementation of SIMD language extensions and compiler support that together add fine-grain vector parallelism to JavaScript. The specification for this language extension is in final stages of adoption by the JavaScript standardization committee and our compiler support is available in two open-source production browsers. The design principles seek portability, SIMD performance portability on various SIMD architectures, and compiler simplicity to ease adoption. The design does not require automatic vectorization compiler technology, but does not preclude it either. The SIMD extensions define immutable fixed-length SIMD data types and operations that are common to both ARM and x86 ISAs. The contributions of this work include type speculation and optimizations that generate minimal numbers of SIMD native instructions from high-level JavaScript SIMD instructions. We implement type speculation, optimizations, and code generation in two open-source JavaScript VMs and measure performance improvements between a factor of 1.7× to 8.9× with an average of 3.3× and average energy improvements of 2.9× on micro benchmarks and key graphics kernels on various hardware, browsers, and operating systems. These portable SIMD language extensions significantly improve compute-intensive interactive applications in the browser, such as games and media processing, by exploiting vector parallelism without relying on automatic vectorizing compiler technology, non-portable na

关键词： parallel processing Hardware Program processors Browsers Games Neon Benchmark testing

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Restructuring and implementations of 2D matrix transpose algorithm using SSE4 vector instructions

Restructuring and implementations of 2D matrix transpose alg...

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international conference on Applied Research in Computer Science and Engineering (ICAR)

作者： Ahmed S. Zekri Faculty of Sciences Alexandria University Alexandria Egypt Department of Mathematics and Computer Science Beirut Arab University Beirut Lebanon

Current general-purpose processors are augmented with vector instructions that can process many elements of matrices and vectors in parallel. Transposing a matrix in-place is a main kernel operation required by many scientific and engineering applications to shuttle data before, during, or after processing. This operation increases the traffic on the memory bus and hence clever techniques such as blocking are required to enhance the performance. In this paper, we present an enhanced version of a previously published algorithm for transposing a matrix on a two-dimensional processor arrays. We restructured this algorithm to fit the one-dimensional vector register architecture augmented to general-purpose CPUs. We implemented the new vector algorithm using Intel SSE4 vector instruction set and compare its performance with the standard sequential algorithm in addition to an already employed implementation of Ekhlundh's algorithm. We also studied the automatic compiler optimizations and their effect on the vectorization of the algorithm. The best of our implementations showed a maximum speedup of 1.6 compared with the sequential algorithm, and an almost equal performance compared with Eklundh's algorithm implementation.

关键词： Registers Program processors Signal processing algorithms parallel processing Yttrium Multicore processing Kernel

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