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Scaling Irregular applications through Data Aggregation and Software Multithreading

Scaling Irregular Applications through Data Aggregation and ...

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IEEE 28th international parallel & distributed processing Symposium (IPDPS)

作者： Morani, Alessandro Tumeo, Antonino Chavarria-Miranda, Daniel Villa, Oreste Valero, Mateo Pacific NW Natl Lab Richland WA 99352 USA NVIDA Santa Clara CA USA Univ Politecn Catalanya Barcelona Supercomputing Ctr Barcelona Spain

ISBN: (纸本)9780769552071

Emerging applications in areas such as bioinformatics, data analytics, semantic databases and knowledge discovery employ datasets from tens to hundreds of terabytes. Currently, only distributed memory clusters have enough aggregate space to enable in-memory processing of datasets of this size. However, in addition to large sizes, the data structures used by these new application classes are usually characterized by unpredictable and fine-grained accesses: i.e., they present an irregular behavior. Traditional commodity clusters, instead, exploit cache-based processor and high-bandwidth networks optimized for locality, regular computation and bulk communication. For these reasons, irregular applications are inefficient on these systems, and require custom, hand-coded optimizations to provide scaling in both performance and size. Lightweight software multithreading, which enables tolerating data access latencies by overlapping network communication with computation, and aggregation, which allows reducing overheads and increasing bandwidth utilization by coalescing fine-grained network messages, are key techniques that can speed up the performance of large scale irregular applications on commodity clusters. In this paper we describe GMT (Global Memory and Threading), a runtime system library that couples software multithreading and message aggregation together with a Partitioned Global Address Space (PGAS) data model to enable higher performance and scaling of irregular applications on multi-node systems. We present the architecture of the runtime, explaining how it is designed around these two critical techniques. We show that irregular applications written using our runtime can outperform, even by orders of magnitude, the corresponding applications written using other programming models that do not exploit these techniques.

关键词： Multithreading PGAS aggregation semantic graph databases Multithreading unified retrieval models Runtime Scale formation agglomeration Dataset Data structures Scaling Irregular

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A Framework to the Design and Programming of Many-Core Focal-Plane Vision Processors

A Framework to the Design and Programming of Many-Core Focal...

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IEEE/IFIP international conference on Embedded and Ubiquitous Computing, EUC

作者： Jones Y. Mori Carlos H. Llanos Michael Hüebner Chair of Embedded Systems for Information Technology (ESIT) Ruhr-University Bochum Germany Universidade de Brasilia Brasilia DF BR Ruhr-Universitat Bochum Bochum Nordrhein-Westfalen DE

The Focal-Plane Image processing area aims to bring processing elements as near as possible to the pixels and to the camera's focal-plane. Most of the works reported in the literature uses only simple processing elements, in general analog ones, with few flexibility. With the technology advances, a new generation of Vision Processors is emerging. It is expected that multi/many-core systems will be integrated to the pixel sensors, offering several opportunities for parallelism exploration, resulting in high performance and flexible processing systems. The programmability is one of the main problems in this area, since most programmers are not able to create parallel algorithms and applications. In this work, we propose a methodology to the design and programming of many-core focal-plane vision processors. The application is described using a Domain Specific Language, from which the parallelism characteristics are extracted. Afterwards, a new abstract model is derived using techniques such as Program Slicing (PS) and Task-Graph Clustering (TGC). The abstract model is then transformed in a SystemC/TLM2.0 description, in order to allow for different timing accuracy simulations. The results of the simulations are used together with an ASIP design tool in order to determine both the microarchitecture of processing elements and the communication structure of the new system. Finally, from the model derived before, a new source code is generated and programmed into the new platform. In this context, the main concepts and ideas are described in this work, as well as some partial results.

关键词： Program processors parallel processing Image processing Programming Arrays Analytical models

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A High-Throughput and Low-Latency parallelization of Window-based Stream Joins on Multicores 12

A High-Throughput and Low-Latency Parallelization of Window-...

引用

12th IEEE international Symposium on parallel and distributed processing with applications (ISPA)

作者： Buono, Daniele De Matteis, Tiziano Mencagli, Gabriele Univ Pisa Dept Comp Sci I-56127 Pisa Italy

ISBN: (纸本)9781479942930

Data Stream processing (DaSP) is a paradigm characterized by on-line (often real-time) applications working on unlimited data streams whose elements must be processed efficiently "on the fly". DaSP computations are characterized by data-flow graphs of operators connected via streams and working on the received elements according to high throughput and low latency requirements. To achieve these constraints, high-performance DaSP operators requires advanced parallelism models, as well related design and implementation techniques targeting multi-core architectures. In this paper we focus on the parallelization of the window-based stream join, an important operator that raises challenging issues in terms of parallel windows management. We review the state-of-the-art solutions about the stream join parallelization and we propose our novel parallel strategy and its implementation on multicores. As demonstrated by experimental results, our parallel solution introduces two important advantages with respect to the existing solutions: (i) it features an high-degree of configurability in order to address the symmetricity/ asymmetricity of input streams (in terms of their arrival rate and window length);(ii) our parallelization provides a high throughput and it is definitely better than the compared solutions in terms of latency, providing an efficient way to perform stream joins on latency-sensible applications.

关键词： Data Stream processing Window-based Stream Joins Continuous Queries Throughput Latency Multicores

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A parallel Algorithm for Compression of Big Next-Generation Sequencing Datasets

A Parallel Algorithm for Compression of Big Next-Generation ...

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IEEE international Symposium on parallel and distributed processing with applications

作者： Sandino Vargas Pérez Fahad Saeed Computer Science Department Western Michigan University Kalamazoo MI 49008 USA Department of Electrical and Computer Engineering Western Michigan University Kalamazoo MI 49008-5329 USA

ISBN: (纸本)9781467379533

The amount of big data from high-throughput NextGeneration Sequencing (NGS) techniques represents various challenges such as storage, analysis and transmission of massive datasets. One solution to storage and transmission of data is compression using specialized compression algorithms. The existing specialized algorithms suffer from poor scalability with increasing size of the datasets and best available solutions can take hours to compress gigabytes of data. Compression and decompression using these techniques for peta-scale data sets is prohibitively expensive in terms of time and energy. In this paper we introduce paraDSRC, a parallel implementation of the DNA Sequence Reads Compression (DSRC) application using a message passing model that presents reduction of the compression time complexity by a factor of O(1/p) (where p is the number of processing units). Our experimental results show that paraDSRC achieves compression times that are 43% to 99% faster than DSRC and compression throughputs of up to 8.4GB/s on a moderate size cluster. For many of the datasets used in our experiments super-linear speedups have been registered making the implementation strongly scalable. We also show that paraDSRC is more than 25.6x faster than comparable parallel compression algorithms. The code is available for free-academic use at .

关键词： Next-Generation Sequencing parallel implementation DSRC MPI big data FASTQ

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Evaluating the Impact of Transactional Characteristics on the Performance of Transactional Memory applications

Evaluating the Impact of Transactional Characteristics on th...

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22nd Euromicro international conference on parallel, distributed, and Network-Based processing (PDP)

作者： Rui, Fernando Castro, Marcio Griebler, Dalvan Fernandes, Luiz Gustavo Pontificia Univ Catolica Rio Grande do Sul GMAP Res Grp FACIN PPGCC Porto Alegre RS Brazil Fed Univ Rio Grande Sul UFRGS Inst Informat Porto Alegre RS Brazil

ISBN: (纸本)9781479927289

Transactional Memory (TM) is reputed by many researchers to be a promising solution to ease parallel programming on multicore processors. This model provides the scalability of fine-grained locking while avoiding common issues of traditional mechanisms, such as deadlocks. During these almost twenty years of research, several TM systems and benchmarks have been proposed. However, TM is not yet widely adopted by the scientific community to develop parallel applications due to unanswered questions in the literature, such as "how to identify if a parallel application can exploit TM to achieve better performance?" or "what are the reasons of poor performances of some TM applications?". In this work, we contribute to answer those questions through a comparative evaluation of a set of TM applications on four different state-of-the-art TM systems. Moreover, we identify some of the most important TM characteristics that impact directly the performance of TM applications. Our results can be useful to identify opportunities for optimizations.

关键词： Transactional memory performance evaluation

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A Framework for Batched and GPU-Resident Factorization Algorithms Applied to Block Householder Transformations 1

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30th international Supercomputing conference on High Performance Computing (ISC High Performance)

作者： Haidar, Azzam Dong, Tingxing Tim Tomov, Stanimire Luszczek, Piotr Dongarra, Jack Univ Tennessee Knoxville TN 37916 USA Oak Ridge Natl Lab Oak Ridge TN USA Univ Manchester Manchester Lancs England

ISBN: (数字)9783319201191

ISBN: (纸本)9783319201191;9783319201184

As modern hardware keeps evolving, an increasingly effective approach to developing energy efficient and high-performance solvers is to design them to work on many small size and independent problems. Many applications already need this functionality, especially for GPUs, which are currently known to be about four to five times more energy efficient than multicore CPUs. We describe the development of one-sided factorizations that work for a set of small dense matrices in parallel, and we illustrate our techniques on the QR factorization based on Householder transformations. We refer to this mode of operation as a batched factorization. Our approach is based on representing the algorithms as a sequence of batched BLAS routines for GPU-only execution. This is in contrast to the hybrid CPU-GPU algorithms that rely heavily on using the multicore CPU for specific parts of the workload. But for a system to benefit fully from the GPU's significantly higher energy efficiency, avoiding the use of the multicore CPU must be a primary design goal, so the system can rely more heavily on the more efficient GPU. Additionally, this will result in the removal of the costly CPU-to-GPU communication. Furthermore, we do not use a single symmetric multiprocessor(on the GPU) to factorize a single problem at a time. We illustrate how our performance analysis, and the use of profiling and tracing tools, guided the development and optimization of our batched factorization to achieve up to a 2-fold speedup and a 3-fold energy efficiency improvement compared to our highly optimized batched CPU implementations based on the MKL library(when using two sockets of Intel Sandy Bridge CPUs). Compared to a batched QR factorization featured in the CUBLAS library for GPUs, we achieved up to 5x speedup on the K40 GPU.

关键词： Graphics processing unit

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international conference on e-health Networking, applications and Services (HealthCom)

作者： Maciej Huk Jolanta Mizera-Pietraszko Department of Computer Science Wroclaw University of Technology Wroclaw Poland Opole University Institute of Mathematics and Informatics Opole Poland

ISBN: (纸本)9781467383264

Classification is a data processing technique of a great significance both for native eHealth systems and web telemedicine solutions. In this sense, artificial neural networks have been widely applied in telerehabilitation as powerful tools to process information and acquire a new medical knowledge. But effective analysis of multidimensional heterogeneous medical data, still poses considerable difficulties. It was shown that processing too many data features simultaneously is costly and has some adverse effects on the resulting models classification properties. Therefore, there is a strong need to develop new techniques for selecting features from the very large data sets that include many irrelevant, or redundant features. This work addresses the context-related feature selection problem from medical data by proposing utility of Sigma-if neural network being an effective model of neurology patients's low-level distributed selective attention mechanisms. Our experiments indicate that a context-aware technique can reduce the average cost of medical data acquisition and data processing as well as it can decrease classification error probability resulting in increasing the overall eHealth systems reliability.

关键词： Neurons Biological neural networks Data processing Data models Training Computer architecture Telemedicine

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Apache Hadoop Yarn Parameter configuration Challenges and Optimization

Apache Hadoop Yarn Parameter configuration Challenges and Op...

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international conference on Soft-Computing and Networks Security (ICSNS)

作者： Bhavin J. Mathiya Vinodkumar L. Desai C. U. Shah University Wadhwan Gujarat India Government Science College Chatrapur Orissa IN

Apache Hadoop Yarn is an open source framework for distributed as well as local storage, processing and analysis of big data on commodity hardware. It provides MapReduce Programming Model, HDFS for distributed File System and Default parameter configuration settings. MapReduce Programming Model provides Mapper and Reducer interface function for parallel computing, processing and execution of program. HDFS provides file system for storing data locally and distributed. Apache Hadoop provides more than hundreds default parameter configuration settings common for all type of clusters and applications. Apache Hadoop Yarn provides functionality that user can customize parameter configuration settings as per their needs through xml file setting as well as in writing program coding for performance tuning of resources likes CPU, I/O, Memory, and Network. Customizing parameter configuration is a black art which required good knowledge of each parameter that what is impact when we change its default values because all parameter are interconnected and affected each other performance. Proper parameter configuration can improve and tune performance as well as misparameter configuration setting can decrease performance of the system. It is challenge that performance tuning of Apache Hadoop Framework through balanced customize parameter configuration setting that it cannot over utilize or under utilize system resources. In this paper we study and analysis of difference type of research paper related to customizing parameter configurations setting for performance tuning of Apache Hadoop jobs and better utilization of available resources. We found that good customization of parameter configuration improve performance compare to default parameter setting.

关键词： Yarn Tuning File systems Memory management Optimization Hardware distributed databases

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Implementation of Particle Filters for Single Target Tracking Using CUDA

Implementation of Particle Filters for Single Target Trackin...

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international conference on Advances in Computing and Communications (ICACC)

作者： Bhavya Goyal Tarun Budhraja Roheet Bhatnagar Chandan Shivakumar Department of Computer science and technology Manipal University Jaipur

In order to implement Sequential Bayesian estimator using Monte carlo simulation and to get rid of limitations of Kalman filter, Particle filtering techniques plays a very crucial role for target tracking applications in state space where Importance sampling approximately distributed by posterior distribution with multimodel feature and robustness to noise. However as the particles becomes very large, the Monte Carlo representation becomes nearly equivalent to analytical description characterization for posterior distributions and has some deficiencies such as high computational cost and low sampling efficiency. Therefore, emerging computing platform, CUDA may be regarded as most appealing platform for such implementaion. Representation provided with set of samples for target distribution of state leads to increase in sampling efficiency so that graphics processing unit (GPUPU) becomes more appealing to use in Particle filter. The modification on mapping architecture are evaluated with qualitative analysis. The proposed design will be 3.5 times faster than direct design.

关键词： Graphics processing units Target tracking Particle filters Mathematical model MATLAB Probabilistic logic Estimation

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Building a distributed key-value store with FPGA-based microservers

Building a distributed key-value store with FPGA-based micro...

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international conference on Field Programmable Logic and applications

作者： Zsolt István David Sidler Gustavo Alonso Dept. of Computer Science Systems Group ETH Zurich Switzerland

Energy efficiency is one of the major challenges in datacenters, and a promising way to tackle it are microservers. These scaled down machines with smaller CPUs, less peripherals and tighter integration improve energy efficiency, but often at the expense of lower performance. In this work we explore the tailoring of standard software components to specialized hardware as a way to get the energy efficiency of microservers without compromising performance. Our specialized microserver implements memcached, a common component in many web stacks, on a cluster of FPGAs. The design explores aspects such as pipelining techniques, tight integration with the network stack, dealing with the memory bottleneck, and shows how to build a complete system out of individual microservers. To our knowledge this is the first stand-alone FPGA-based solution that can be used as a drop-in replacement for the software version. Beyond the per-node performance, in this demo we focus on the replication and the integration aspects of our system. We run a common benchmark on a PostgreSQL database with a two-node deployment of FPGAs acting as a cache for query results.

关键词： Hardware Field programmable gate arrays Benchmark testing Software Workstations Pipeline processing Databases

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