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检索条件"任意字段=International Conference on Parallel and Distributed Processing Techniques and Applications"

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parallel Video processing techniques for Surveillance applications

Parallel Video Processing Techniques for Surveillance Applic...

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international conference on Computational Science and Computational Intelligence (CSCI)

作者： Leonidas Deligiannidis Hamid R. Arabnia Wentworth Institute of Technology Computer Science Boston MA USA University of Georgia Computer Science Athens GA USA

ISBN: (纸本)9781479930111

In this paper we present several solutions to Security Surveillance and their applications while utilizing parallel processing for improved performance. The algorithms presented in this paper are explained in detail and their implementations are provided for free for educational purposes. These algorithms with their implementations are being taught in our parallel processing course utilizing NVidia's Cuda language and framework. We chose the topic of Security Surveillance in our parallel processing course because the results are visual and applicable in many situations such as Surveillance of parking lots (monitoring our car for example), dormitory rooms, offices, etc. Image processing techniques and algorithms are discussed in this paper, and extended to real-time high definition video processing focusing on surveillance.

关键词： Graphics processing units Instruction sets Detectors Surveillance Kernel Filtering algorithms Cameras

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A Novel Weighted Dynamic Time Warping for Light Weight Speaker-Dependent Speech Recognition in Noisy and Bad Recording Conditions

A Novel Weighted Dynamic Time Warping for Light Weight Speak...

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2nd international conference on Mechanical Design and Power Engineering (ICMDPE 2013)

作者： Zhang, Xianglilan Sun, Jiping Huang, Xuhui Luo, Zhigang Natl Univ Def Technol Sch Comp Sci Natl Lab Parallel & Distributed Proc Changsha 410073 Hunan Peoples R China Univ Waterloo David R Cheriton Sch Comp Sci Waterloo N2L 3G1 ON Canada Natl Univ Def Technol Sch Comp Sci Natl Lab parallel & distributed Proc Changsha 410073 Peoples R China

ISBN: (纸本)9783038350019

Lightweight speaker-dependent (SD) automatic speech recognition (ASR) is a promising solution for the problems of possibility of disclosing personal privacy and difficulty of obtaining training material for many seldom used English words and (often non-English) names. Dynamic time warping (DTW) algorithm is the state-of-the-art algorithm for small foot-print SD ASR applications, which have limited storage space and small vocabulary. In our previous work, we have successfully developed two fast and accurate DTW variations for clean speech data. However, speech recognition in adverse conditions is still a big challenge. In order to improve recognition accuracy in noisy and bad recording conditions, such as too high or low recording volume, we introduce a novel weighted DTW method. This method defines a feature index for each time frame of training data, and then applies it to the core DTW process to tune the final alignment score. With extensive experiments on one representative SD dataset of three speakers' recordings, our method achieves better accuracy than DTW, where 0.5% relative reduction of error rate (RRER) on clean speech data and 7.5% RRER on noisy and bad recording speech data. To the best of our knowledge, our new weighted DTW is the first weighted DTW method specially designed for speech data in noisy and bad recording conditions.

关键词： Computing Methodologies Weighted DTW Natural Language processing Speech Recognition and Feature Index

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SHEPARD: Scheduling on Heterogeneous Platforms Using Application Resource Demands

SHEPARD: Scheduling on Heterogeneous Platforms Using Applica...

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Euromicro conference on parallel, distributed and Network-Based processing

作者： Eoghan ONeill John McGlone Peter Milligan Peter Kilpatrick SAP Next Business and Technology Electrical Engineering and Computer Science Queen's University Belfast

Heterogeneous computing technologies, such as multi-core CPUs, GPUs and FPGAs can provide significant performance improvements. However, developing applications for these technologies often results in coupling applications to specific devices, typically through the use of proprietary tools. This paper presents SHEPARD, a compile time and run-time framework that decouples application development from the target platform and enables run-time allocation of tasks to heterogeneous computing devices. Through the use of special annotated functions, called managed tasks, SHEPARD approximates a task's performance on available devices, and coupled with the approximation of current device demand, decides which device can satisfy the task with the lowest overall execution time. Experiments using a task parallel application, based on an in-memory database, demonstrate the opportunity for automatic run-time task allocation to achieve speed-up over a static allocation to a single specific device.

关键词： Kernel Performance evaluation Graphics processing units Resource management Mathematical model Equations Dictionaries

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Time synchronization (IEEE 1588) and seamless communication redundancy (IEC 62439-3) techniques for Smart Grid Substations

Time synchronization (IEEE 1588) and seamless communication ...

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12th IET international conference on Developments in Power System Protection, DPSP 2014

作者： Guo, Hao Crossley, Peter Electrical Energy and Power Systems Group School of Electrical and Electronic Engineering University of Manchester United Kingdom

ISBN: (纸本)9781849198349

Communication is a key factor to the success of the future Smart Grid. Among various technologies, Ethernet is a predominant one for Local Area Network (LAN) communication due to its low cost and high speed and Power Substations will see increasing use of Ethernet in the protection & control sector. The Ethernet based IEEE 1588- 2008 time synchronization protocol can realize sub-micro second accuracy and can be regarded as a good alternative to the conventional synchronization method based on distributed GPS receivers. Meanwhile, as the Ethernet will become the carrier of protection and control information, it is necessary to ensure fast or even zero recovery time when a communication failure occurs, which can be satisfied by IEC 62439-3 parallel Redundancy Protocol (PRP) and High-Available Seamless Ring (HSR) protocol. This paper describes how IEEE 1588 and IEC 62439-3 PRP protocols, based on opposite network path knowledge, can be combined to achieve accurate time synchronization and analyzes the simulation results to give recommendations on future applications of these two protocols.

关键词： Ethernet

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Hybrid Classification of Resistors through Image processing

Hybrid Classification of Resistors through Image Processing

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Euromicro conference on parallel, distributed and Network-Based processing

作者： Romina Molina Pablo Federigi Veronica Gil-Costa Marcela Printista National University of San Luis Argentina UNSL and CONICET Argentina

Digital image processing consists of a set of techniques for contrast enhancement, noise reduction, image sharpening, segmentation, object recognition, and quantitative analysis of the image. In this work, we focus on object recognition on images containing electronic resistors. Our system classifies those resistors according to the colored bands of the resistors found in the image. This paper will introduce the system, presenting an architecture that leads to a high performance image processing system and describing a hybrid programming model, through the combined operation of processes and threads to meet the requirements of that system. In addition, the paper presents some discussion about the performance on different resources configuration on a cluster of multi-core nodes.

关键词： Resistors Message systems Image color analysis Clustering algorithms Resistance Digital images

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Improve User Experience on Web for Machine Translation System using Storm 4

Improve User Experience on Web for Machine Translation Syste...

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IEEE Fourth international conference on Big Data and Cloud Computing (BdCloud)

作者： Ahmad, Rashid Kumar, Pawan Kumar, Ashutosh Sinha, Mukul K. Chaudhary, B. D. Int Inst Informat Technol LTRC Hyderabad Andhra Pradesh India Expert Software Consultants Ltd New Delhi India Indian Inst Technol Sch Comp & Elect Engn Mandi India

ISBN: (纸本)9781479967193

A transfer based Machine Translation (MT) system is a large complex functional application where the job completion time is proportional to job size. When these applications are deployed on web with increasing translation load web user experience degrades. The end user has to wait unusually longer to get his first visible response. Generic layer 3 load balancing techniques does not help to improve the response time as each job is assigned similar compute resources irrespective of job size. This paper presents an engineering approach to deploy MT system on cloud platform using Storm, a distributed computing framework. This scheme, by utilizing the inherent parallelism of a functional application, not only reduces the job completion time considerably but it, also as a web application, gives very good user experience, viz., the first visible response time within an acceptable time limit, and the subsequent responses well before the user finishes perusing the preceding response. Using Storm framework a translation job is split into multiple job partitions and is streamed into the storm cluster such that first job partitions of all jobs are processed before the second partitions, i.e., all nth partitions of all jobs are processed before (n+1)th partitions. Thus machine translation system is able to produce translation output as a continuous stream, sentence by sentence, as soon as each sentence gets translated. The system maintains flow rate of translated sentences stream high enough so that the next translated sentence is produced well before the end user finishes reading the previous sentence, thereby providing very good user experience. There is a class of natural language processing (NLP) applications, viz., machine translation systems, text to speech systems, speech recognition systems, etc., that are functional in nature, and this engineering approach would be equally applicable to them as well.

关键词： NLP Machine Translation Storm Framework Stream processing Interactive Response Throughput Performance

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GRapid: A compilation and runtime framework for rapid prototyping of graph applications on many-core processors

GRapid: A compilation and runtime framework for rapid protot...

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international conference on parallel and distributed Systems (ICPADS)

作者： Da Li Srimat Chakradhar Michela Becchi University of Missouri-Columbia NEC Laboratories America

Many applications use graphs to represent and analyze data, but the effective deployment of graph algorithms on many-core processors is still a challenge. Many-core devices offer higher peak performance than multi-core devices; however, many-core programming is still a specialized skill. While compilation and runtime frameworks for parallelizing graph applications on multi-core CPUs exist, there is still a need for comparable frameworks for many-core devices. We propose GRapid: a compilation and runtime framework that generates efficient parallel implementations of generic graph applications for multi-core CPUs, NVIDIA GPUs and Intel Xeon Phi. applications are expressed using a platform-agnostic programming API. Our source-to-source compiler performs platform-specific code transformations and optimizations, handles data transfers between the host and the coprocessor, and generates several functionally-equivalent code variants for the target platform. Our runtime library provides an efficient dynamic memory management scheme for applications where the graph topology is modified during processing. We used the proposed framework to rapidly generate efficient implementations of four graph applications on different target processors. Such rapid prototyping and re-targeting capability has obvious programmability advantages, but it can also be used to quickly identify target processors that better match the application's computational needs.

关键词： Data structures Runtime Synchronization Containers Programming Memory management parallel processing

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Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-Based applications

Rediscovering Logarithmic Diameter Topologies for Low Latenc...

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Euromicro conference on parallel, distributed and Network-Based processing

作者： Carlo Condo Maurizio Martina Massimo Ruo Roch Guido Masera Electronics and Telecommunications Department Politecnico di Torino Torino Italy

Low-latency Network-on-Chip (NoC) applications have tight constraints on the clock budget to perform communication among nodes. This is a critical aspect in NoC-based designs where the number of clock cycles spent for communication depends mainly on the topology and on the routing algorithm. This work deals with logarithmic diameter topologies, that were proposed for computer networks, and shows that an optimal shortest-path routing algorithm can be efficiently implemented on this kind of topologies by means of a very simple circuit. The proposed circuit is then exploited to reduce the area and the power consumption of a recently proposed NoC-based design. Experimental results show that the proposed circuit allows for a reduction of about 14% and 10% for area and power consumption respectively, with respect to a shortest-path routing-table-based design.

关键词： Topology Computer architecture Routing Complexity theory Decoding Network topology Power demand

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XML Data Interface and PMU Testing applications for Synchrophasor Estimation with a Reconfigurable Controller 49

XML Data Interface and PMU Testing Applications for Synchrop...

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49th international Universities Power Engineering conference (UPEC)

作者： Katsimichas, Anastasis Brogan, Paul Laverty, David Queens Univ Belfast EPIC Belfast BT7 1NN Antrim North Ireland

ISBN: (纸本)9781479965571

Phasor Measurement Unit (PMU) technology has rapidly improved over the last two decades. This development allowed a number of conventional protocols, both open and proprietary, to be written. Optimised communication and implementation techniques are sought by academia. This motivation has resulted in university projects, such as The OpenPMU project. The aim is to create a completely open source system that will be cost efficient, reliable, modular and platform independent. The discussed work is focused on the detailed description of a data interface XML based communication tool. The outlined schema is used to exchange data between the acquisition system and the phase estimation algorithm of a PMU. Its many advantages establish it as a flexible schema for transmitting sampled data irrespective of hardware or software implementation. The OpenPMU system is based on hardware implementations that use freely available DAQ devices and aim to develop a low cost alternative to commercial PMU's. The hardware described in this paper is based on a National Instruments field programmable gate array (FPGA) reconfigurable controller (cRIO) that due to its parallel nature can perform different processing operations at the same time. This results in higher speed and accuracy and should provide the benchmark for testing various existing and future OpenPMU implementations.

关键词： OpenPMU phasor measurement unit field programmable gate array National Instruments phasor estimation

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Optimizing message-passing on multicore architectures using hardware multi-threading

Optimizing message-passing on multicore architectures using ...

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Euromicro conference on parallel, distributed and Network-Based processing

作者： Daniele Buono Tiziano De Matteis Gabriele Mencagli Marco Vanneschi Department of Computer Science University of Pisa Pisa Italy

Shared-memory and message-passing are two opposite models to develop parallel computations. The shared-memory model, adopted by existing frameworks such as OpenMP, represents a de-facto standard on multi-/many-core architectures. However, message-passing deserves to be studied for its inherent properties in terms of portability and flexibility as well as for its better ease of debugging. Achieving good performance from the use of messages in shared-memory architectures requires an efficient implementation of the run-time support. This paper investigates the definition of a delegation mechanism on multi-threaded architectures able to: (i) overlap communications with calculation phases, (ii) parallelize distribution and collective operations. Our ideas have been exemplified using two parallel benchmarks on the Intel Phi, showing that in these applications our message-passing support outperforms MPI and reaches similar performance compared to standard OpenMP implementations.

关键词： Message systems Hardware Libraries Multicore processing parallel processing Context

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