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Accelerating Matrix Power Operations with GPUs 2021

Accelerating Matrix Power Operations with GPUs

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4th international conference on Electronics, Communications and Control Engineering (ICECC)

作者： Wu, Lezhou Northeastern Univ Coll Informat Sci & Engn Shenyang 110819 Liaoning Peoples R China

ISBN: (纸本)9781450389129

Many-core framework, represented by Graphic processing Unit (GPU), has been becoming more popular in scientific computing and data analysis, and Compute Unified Device Architecture (CUDA) allows developers to carry out computation on GPUs more conveniently. Matrix operation is one of the most important application scenarios of GPU computation and CUDA, widely appearing in domains like graph applications and artificial intelligence. This paper focuses on accelerating matrix power operation (MPO) process, which appears in many engineering problems and may be time-consuming when the scale of matrixes is large, with GPUs and CUDA. In this paper, three techniques are used to speed up the MPO process: matrix parallel reduction, matrix parallel multiplication and CUDA dynamic parallelism. The experiments were carried out on NVIDIA RTX 2080 Super and Intel(R) Core(TM) i7-10750H. The code is compiled and executed in Visual Studio 2019 community, the GPU driver version is 461.40, the CUDA version is 11.1, and the NVCC version is 11.1.74. With all three techniques, the MPO process can get hundreds of times speedup compared with the sequential multiplication process executed by Eigen library, even though the code of algorithm is hardly optimized. Moreover, with the number of power increasing, the efficiency of algorithm can be even higher because of the relatively fixed time consumed in data transmission and GPU memory allocation.

关键词： GPU CUDA Matrix power operation parallel reduction Dynamic parallelism Matrix parallel multiplication

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Automatic tuning of master/worker applications

Automatic tuning of master/worker applications

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11th international Euro-Par conference

作者： Morajko, A César, E Caymes-Scutari, P Margalef, T Sorribes, J Luque, E Univ Autonoma Barcelona Dept Comp Sci Bellaterra 08193 Spain

ISBN: (纸本)3540287000

The Master/Worker paradigm is one of the most commonly used by parallel/distributed application developers. This paradigm is easy to understand and is fairly close to the abstract concept of a wide range of applications. However, to obtain adequate performance indexes, such a paradigm must be managed in a very precise way. There are certain features, such as data distribution or the number of workers, that must be tuned properly in order to obtain such performance indexes, and in most cases they cannot be tuned statically since they depend on the particular conditions of each execution. In this context, dynamic tuning seems to be a highly promising approach since it provides the capability to change the parameters during the execution of the application to improve performance. In this paper, we demonstrate the usage of a dynamic tuning environment that allows for adaptation of the number of workers based on a theoretical model of Master/Worker behavior. The results show that such an approach significantly improves the execution time when the application modifies its behavior during execution.

关键词： parallel processing systems

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A hybrid performance modeling approach for adaptive algorithm selection on hierarchical clusters

A hybrid performance modeling approach for adaptive algorith...

引用

2010 ACS/IEEE international conference on Computer Systems and applications, AICCSA 2010

作者： Nasri, Wahid Achour, Sami Higher School of Sciences and Techniques of Tunis Department of Computer Science 1008 Tunis Tunisia

ISBN: (纸本)9781424477159

Recent advances in parallel and distributed computing have made it very challenging for programmers to reach the performance potential of current systems. In addition, recent advances in numerical algorithms and software optimizations have tremendously increased the number of alternatives for solving a problem, which further complicates the software tuning process. Indeed, no single algorithm can represent the universal best choice for efficient solution of a given problem on all compute substrates. In this paper, we develop a framework that addresses the design of efficient parallel algorithms in hierarchical computing environments. More specifically, given multiple choices for solving a particular problem, the framework uses a judicious combination of analytical performance models and empirical approaches to automate the algorithm selection by determining the most suitable execution scheme expected to perform the best at the specific setting. Preliminary experimental results obtained by implementing two different numerical kernels demonstrated the interest of the hybrid performance modeling approach integrated in the framework.

关键词： Adaptive algorithms

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LARGE MEASUREMENT REGRESSION: HIERARCHICAL LEAST SQUARES MULTISPLITTING

LARGE MEASUREMENT REGRESSION: HIERARCHICAL LEAST SQUARES MUL...

引用

IEEE international Instrumentation and Measurement Technology conference (I2MTC)

作者： Inghelbrecht, Gilles Barbe, Kurt Vrije Univ Brussel Dept Math DWIS Res Grp Digital Math DIMA Pl Laan 2 B-1050 Brussels Belgium

ISBN: (纸本)9781538634608

Various measurement applications rely on indirect measurements such that the measurand is mapped through a mathematical model to the parameters of interest. Hence, measurement engineers rely on statistical models for which optimal estimators lead to sharp uncertainty bounds. Within the least squares (LS) estimation, these parameters are estimated through a regression problem. The presence of dynamics, multiple sensors and high sampling rates lead to an increased model complexity and hence high dimensional regression matrices. This paper aims to solve such massive regression problems efficiently. We revisit Reliant's Least Squares Multisplitting (LSMS) technique aimed at solving the ordinary least squares problem in parallel. The global least squares solution is replaced by an equivalent set of local smaller-sized least squares problems. At every iteration step the local solutions are recombined using an appropriate weighting scheme. Only if the scheme is convergent, it will allow a scalable and highly parallel implementation aimed at distributed systems. However, there exist regression designs for which the LSMS is divergent for each partition larger than 2. Hence, we propose a novel technique, the Hierarchical LSMS, in order to obtain the same number of parallel blocks, for which convergence is ascertained. We present its numerical properties and illustrate the technique with dedicated numerical simulations and an application within the domain of signal processing.

关键词： Digital signal processing high-rate measurement problems multisplitting parallelization least squares

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Performance Analysis of FPGA Implementation of 4 x 4 Vedic Multiplier using different adder architectures 2

Performance Analysis of FPGA Implementation of 4 x 4 Vedic M...

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2nd international conference on Electrical, Electronics, Information and Communication Technologies, ICEEICT 2023

作者： Deepa, M. Varssha, B. Srivarsa, T. Hariprasath, K. PSG Institute of Technology and Applied Research Department of Electronics and Communication Engineering Coimbatore India

ISBN: (纸本)9798350397635

High-speed applications, such as signal processing and image processing, require fast computations, which in turn require high-speed multiplications. Multipliers are the most essential components in signal processing systems and are used for various operations such as filtering, modulation, coding, and decoding. Therefore, the development of high-speed multipliers is crucial for meeting the demands of modern digital signal processing applications. There are various techniques used to design high-speed multipliers, such as parallel multipliers, array multipliers, and carry save multipliers. These techniques help in producing fast and efficient multipliers that are capable of meeting the demands of high speed applications. The multiplier blocks are considered as one of the major hardware blocks causing a bottleneck in terms of power dissipation and delay in most of the fast processing systems. Multiplication operation consumes high power and more hardware resources when compared to other arithmetic operations. This paper highlights the design and FPGA implementation of 4-bit Binary Vedic multiplier, which results in less power dissipation and low propagation delay when contrasted with conventional type of multipliers. The simulation of the vedic multipliers is carried out using Xilinx 2018 software with the HDL Verilog. The design is implemented and synthesized using FPGA board (Zed board). Also, the output is visualized using the board The performance analysis is conducted for the Vedic Binary multiplier designed with various adder architectures. © 2023 IEEE.

关键词： Digital signal processing

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A distributed Storage System for System Logs Based on Hybrid Compression Scheme 21

A Distributed Storage System for System Logs Based on Hybrid...

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21st IEEE international Symposium on parallel and distributed processing with applications, 13th IEEE international conference on Big Data and Cloud Computing, 16th IEEE international conference on Social Computing and Networking and 13th international conference on Sustainable Computing and Communications, ISPA/BDCloud/SocialCom/SustainCom 2023

作者： Chang, Baoming Zhou, Fengxi Wang, Zhaoyang Wen, Yu Zhang, Boyang Institute of Information Engineering Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences School of Cyber Security Beijing China

ISBN: (纸本)9798350329223

Modern enterprises are facing a massive threat from Advanced Persistent Threats (APTs), which have risen to be one of the most dangerous challenges in recent years. Since system logs capture the complex causality dependencies between system entities, they have become the primary data source for countering APTs. However, as modern computer systems get more complicated, system logs can pile up in large quantities. Besides, APTs are sophisticated and persistent cyber attacks that can remain hidden in the target for a long time and constantly steal private data. System logs need to be collected and stored for a long duration to enable a complete analysis of APTs. Such a vast amount of log data is challenging for enterprises to store and manage. There are two mainstream solutions for reducing storage overhead. Data compression methods provide an intuitive idea. However, they are designed for general text and lack optimization for system logs. Another solution considers log reduction, which removes redundant system events recorded in system logs by predefined rules. Unfortunately, they are tailored for specific kinds of redundant information, resulting in limited applicability. Realizing that these two solutions adopt two distinct perspectives to reduce storage overhead, they are complementary. Data compression methods shrink the size of log data from their binary form. Log reduction starts from the semantic information of system logs and removes redundant information to reduce storage overhead. Combining both methods maximizes storage efficiency. In this paper, we propose a distributed storage system based on a hybrid compression scheme. To address the above deficiencies, we first identify and merge redundant system events by analyzing and tracing the information flow rather than based on rules. Then, we apply log parsing to preprocess log entries for further storage efficiency. Besides, we design a distributed architecture to optimize compression and eliminate repeated

关键词： Digital storage

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Transnet Architecture and Logistical Networking for distributed Storage 17

Transnet Architecture and Logistical Networking for Distribu...

引用

17th international conference on parallel and distributed Computing Systems, PDCS 2004

作者： Beck, Micali Ding, Ying Moore, Terry Plank, James S. Logistical Computing and Internetworking Laboratory Computer Science Department University of Tennessee United States

ISBN: (纸本)9781618398185

This paper addresses the possibility that IP, in the role of the common service, is not as general as is needed in order-to directly address application requirements, including scalable storage services, that go beyond simple datagram delivery. We propose to generalize the view of layer 2 to include local storage and processing services, and to situate. a new common protocol between the local and network layers in the current network stack. Since a protocol at this layer would provide an abstraction of services for data that is in transit at the intermediate node, we propose to call it the transit layer Our view is that a transit layer protocol that abstracts the particular characteristics of different technologies at the local layer, while being more general and sitting below the network layer in the stack, would exhibit greater deployment scalability and provide a broader foundation for network interoperability than IP. We present an account of scalable storage middleware developed under the auspices of the Logistical Networking project as an overlay implementation of transit layer functionality over the current Internet. © (2004) by the international Society for Computers and Their applications All rights reserved.

关键词： Network layers

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Ambient clouds: Reactive asynchronous collections for mobile ad hoc network applications

Ambient clouds: Reactive asynchronous collections for mobile...

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13th IFIP WG 6.1 international conference on distributed applications and Interoperable Systems, DAIS 2013, Held as Part of the 8th international Federated conference on distributed Computing techniques, DisCoTec 2013

作者： Pinte, Kevin Lombide Carreton, Andoni Gonzalez Boix, Elisa De Meuter, Wolfgang Software Languages Lab. Vrije Universiteit Brussel Pleinlaan 2 1050 Brussel Belgium

ISBN: (纸本)9783642385407

In MANET applications, a common pattern is to maintain and query time-varying collections of remote objects. Traditional approaches require programmers to manually track the connectivity state of these remote objects and adding or removing them from local collections on a per-object basis. Queries over these collections have to be manually recomputed whenever the collection or its elements change. The code for maintaining these ad-hoc collections is scattered across the application code and leads to bugs hindering the application development process. In this paper, we propose an object-oriented abstraction called ambient clouds: a collection of objects whose contents are implicitly updated when changes occur. Ambient clouds can be queried and composed using reactive standard query operators. We show how ambient clouds ease the development of a collaborative peer-to-peer drawing application. © 2013 IFIP international Federation for Information processing.

关键词： Mobile ad hoc networks

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Algorithms and Architectures for parallel processing 1

引用

丛书名： Lecture Notes in Computer Science

1000年

作者： Ching-Hsien Hsu Laurence T. Yang Jong Hyuk Park Sang-Soo Yeo

ISBN: (数字)9783642131363

ISBN: (纸本)9783642131356

It is our great pleasure to present the proceedings of the symposia and workshops on parallel and distributed computing and applications associated with the ICA3PP 2010 conference. These symposia and workshops provide vibrant opportunities for researchers and industry practitioners to share their research experience, original research results and practical development experiences in the new challenging research areas of parallel and distributed computing technologies and applications. It was the first time that the ICA3PP conference series added symposia and wo- shops to its program in order to provide a wide range of topics that extend beyond the main conferences. The goal was to provide a better coverage of emerging research areas and also forums for focused and stimulating discussions. With this objective in mind, we selected three workshops to accompany the ICA3PP 2010 conference: • FPDC 2010, the 2010 international Symposium on Frontiers of parallel and distributed Computing • HPCTA 2010, the 2010 international Workshop on High-Performance Computing, Technologies and applications • M2A 2010, the 2010 international Workshop on Multicore and Mul- threaded Architectures and Algorithms Each of the symposia / workshops focused on a particular theme and complemented the spectrum of the main conference. All papers published in the workshops proce- ings were selected by the Program Committee on the basis of referee reports. Each paper was reviewed by independent referees who judged the papers for originality, quality, contribution, presentation and consistency with the theme of the workshops.

关键词： Computer System Implementation Algorithm Analysis and Problem Complexity Artificial Intelligence Software Engineering Information Storage and Retrieval Computation by Abstract Devices

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A Data-Centric Approach for Analyzing Large-Scale Deep Learning applications 23

A Data-Centric Approach for Analyzing Large-Scale Deep Learn...

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24th international conference on distributed Computing and Networking (ICDCN)

作者： Vineet, S. Sai Joseph, Natasha Meena Korgaonkar, Kunal Paul, Arnab K. BITS Pilani KK Birla Goa Campus Zuarinagar Goa India

ISBN: (纸本)9781450397964

Over the past two decades, deep learning techniques have emerged as an immensely powerful technology, with break-through in computer vision, speech to text technologies, natural language processing and many more such fields. As neural networks grow in size and capacity, they require higher compute power and larger datasets to converge to a model with higher accuracy. In this poster, we present a data-centric approach to studying the system level requirements (GPU utilization, CPU utilization, I/O) of deep learning training workloads, and uncover a few insights that help us understand the nature of deep learning training workloads. We analyse three datasets found in industry, academia and national laboratories to understand the requirements and properties of deep learning training workloads.

关键词： Deep Learning Supercomputers Resource Utilization

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