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检索条件"任意字段=International Conference on Parallel and Distributed Processing Techniques and Applications"

共 11317 条记录，以下是771-780 订阅

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Hardware-Efficient Ultrasonic Entrance Counting: Comparing Different Machine Learning Approaches 26

Hardware-Efficient Ultrasonic Entrance Counting: Comparing D...

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26th international conference on Pattern Recognition / 8th international Workshop on Image Mining - Theory and applications (IMTA)

作者： Langer, Tim Waschneck, Bernd Partzsch, Johannes Kelber, Florian Mayr, Christian Infineon Technol Dresden GmbH Co KG Dresden Germany Fraunhofer Inst Integrated Circuits Div Engn Adapt Syst Dresden Dresden Germany Tech Univ Dresden Chair Highly Parallel VLSI Syst & Neuro Microelec Dresden Germany

ISBN: (数字)9781665490627

ISBN: (纸本)9781665490627

In this work, the classification of walking direction based on ultrasonic signals has been examined for entrance counting. Feed-forward and recurrent neural network architectures as well as simpler machine learning techniques have been investigated and compared with classical signal processing techniques. Using only a single ultrasonic receiver, the focus was set on the development of a hardware-efficient system concept. Different ultrasonic measurement methods in time and frequency domain have been compared with the perspective of a holistic energy optimization. The analysis of the system's hardware efficiency was completed by an estimation of algorithmic latency, energy and storage consumption based on the arithmetic of the classification algorithms. All algorithms showed an estimated energy consumption of less than 10 mu J for a single inference on a state-of-the-art implementation of an ARM (R) Cortex (R) M4F micro-controller, which was found to be negligible compared to the energy of the measurement principle. Compared to other sensor types and multi-sensor systems, a state-of-the-art test accuracy of 99.72% could be achieved for differentiating between the two entrance directions of a present person and the absence of a person.

关键词： Entrance Counting Ultrasound Machine Learning Edge Computing Low Power TinyML Smart Buildings

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Efficient, Reliable, and Scalable distributed Data processing Based on Hadoop

Efficient, Reliable, and Scalable Distributed Data Processin...

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Power, Electrical Engineering, Electronics and Control (PEEEC), international conference on

作者： Yingwei Liang Taipeng Zhu Chenghui Liu Yue Chen Yufei Yang CSG Guangdong Power Grid Co. Ltd. Information Center Guangzhou Guangdong China

ISBN: (数字)9798350378917

ISBN: (纸本)9798350378924

With the rapid growth of information technology and the intelligent upgrading of terminal devices, the amount of data in modern society is showing an explosive growth trend. These data are not only large-scale, but also structurally diverse. This data characteristic poses significant challenges to traditional data processing and storage methods. Although traditional distributed database and data warehouse technologies can to some extent cope with large-scale data processing, efficiency and flexibility are still limited when dealing with unstructured and massive data. In this context, the emergence of Hadoop and Map Reduce technologies has provided new solutions for large-scale data processing. Hadoop has become one of the mainstream technologies for handling big data due to its simple programming model, good scalability, and powerful fault tolerance. This article designs a distributed data processing system based on Hadoop, which fully utilizes the efficiency, high reliability, and high scalability of Hadoop, aiming to meet the needs of large-scale data processing. The experimental results show that the system in this paper has demonstrated excellent performance and stability in practical applications, and can process massive data, providing an effective solution for large-scale data processing.

关键词： Fault tolerance Scalability Fault tolerant systems distributed databases Programming parallel processing Data processing Reliability engineering Stability analysis Real-time systems

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DDCEL: Efficient distributed Doubly Connected Edge List for Large Spatial Networks

DDCEL: Efficient Distributed Doubly Connected Edge List for ...

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international conference on Mobile Data Management

作者： Laila Abdelhafeez Amr Magdy Vassilis J. Tsotras Computer Science and Engineering Center for Geospatial Sciences University of California Riverside

The Doubly Connected Edge List (DCEL) is a popular data structure for representing planar subdivisions and is used to accelerate spatial applications like map overlay, graph simplification, and subdivision traversal. Current DCEL implementations assume a standalone machine environment, which does not scale when processing the large dataset sizes that abound in today’s spatial applications. This paper proposes a distributed Doubly Connected Edge List (DDCEL) data structure extending the DCEL to a distributed environment. The DDCEL constructor undergoes a two-phase paradigm to generate the subdivision’s vertices, half-edges, and faces. After spatially partitioning the input data, the first phase runs the sequential DCEL construction algorithm on each data partition in parallel. The second phase then iteratively merges information from multiple data partitions to generate the shared data structure. Our experimental evaluation with real data of road networks of up to 563 million line segments shows significant performance advantages of the proposed approach over the existing techniques.

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Dynamic Allocation of Processor Cores to Graph applications on Commodity Servers

Dynamic Allocation of Processor Cores to Graph Applications ...

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international conference on parallel Architecture and Compilation techniques (PACT)

作者： Lucia Pons Julio Sahuauillo Timothy M. Jones Universitat Politè cnica de València Valencia Valencia Spain University of Cambridge Cambridge United Kingdom

Graph processing is increasingly adopted to solve problems that span many application domains, including scientific computing, social networks, and big-data analytics. These applications present particular features (huge working sets and irregular scalability) that make the default Linux scheduler, which adopts a time-sharing policy to provide a fair scheduler, perform poorly when co-locating multiple graph applications in the same processor. This work focuses on maximizing processor utilization, which is a major concern of current data centers. To this end, we propose AFAIR, a flexible scheduling policy that allocates multiple graph applications on the same processor and assigns a fraction of the cores exclusively to each application instead of sharing them. Moreover, AFAIR dynamically adds/removes cores to the running applications, adapting the number of threads used for parallel execution to balance memory load. This allows AFAIR to achieve almost perfect fairness, on average 95%.

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Malleability techniques for HPC Systems 14th

Malleability Techniques for HPC Systems

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14th international conference on parallel processing and Applied Mathematics, PPAM 2022

作者： Carretero, Jesus Exposito, David Cascajo, Alberto Montella, Raffaele Universidad Carlos III de Madrid. Departamento de Informática Madrid Leganes Spain Naples Italy

ISBN: (纸本)9783031304446

Abstract The current static usage model of HPC systems is becoming increasingly inefficient due to the continuously growing complexity of system architectures, combined with the increased usage of coupled applications, the need for strong scaling with extreme scale parallelism, and the increasing reliance on complex and dynamic workflows. Malleability techniques adjust resource usage dynamically for HPC systems and applications to extract maximum efficiency. In this paper, we present FlexMPI, a tool being developed in the ADMIRE project that provides an intelligent global coordination of resource usage at the application level. FlexMPI considers runtime scheduling of computation, network usage, and I/O across all system architecture components. It can optimize the exploitation of HPC and I/O resources while minimizing the makespan of applications in many cases. Furthermore, FlexMPI provides facilities such as application world recomposition to generate a new consistent state when processes are added or removed to the applications, data redistribution to the new application world, and I/O interference detection to migrate congesting processes. We also present an environmental use case co-designed using FlexMPI. The evaluation shows its adaptability and scalability. © 2023, The Author(s), under exclusive license to Springer Nature Switzerland AG.

关键词： Complex networks

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Efficient parallel processing of Stereoscopic Video Streams for Low-Latency applications

Efficient Parallel Processing of Stereoscopic Video Streams ...

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international conference on Computing and Networking Technology (ICCNT)

作者： H R Manjunath V.S. Gaikwad T. Kuppuraj Takveer Singh D Little Femilin Jana Amit Kansal School of Engineering and Technology Physics JAIN (Deemed to be University) Bangalore Karnataka Computer Engineering Vishwakarma Institute of Technology Pune India Department of Computer Applications Karpagam Academy of Higher Education Coimbatore India Centre of Research Impact and Outcome Chitkara University Rajpura Punjab India Department of Science and Humanities Prince Shri Venkateshwara Padmavathy Engineering College Chennai India Quantum University Research Centre Quantum University

ISBN: (数字)9798350370249

ISBN: (纸本)9798350370270

Streams for video conferencing and interactive streaming applications. By using exploiting the spatial and temporal redundancies of stereoscopic video sequences, the proposed technique leverages GPUs to technique and encodes the video streams in parallel, decreasing the full latency from video shooting to encoding for transmission. This technique utilizes parallel processing to lessen latency by means of processing more than one frame simultaneously, utilizing facts systems to make the most interface dependencies and calculating the audio-video synchronization in a single bypass. The technique also uses motion estimation techniques to reduce the range of layers of the video coding, and a temporal scalability scheme to lessen temporal artifacts. Moreover, the technique applies the excessive-performance encoding of the LHE codec to enhance the compression performance and latency for stereoscopic video streaming. Ultimately, the resulting latency of the proposed approach is validated to be superior to frame-with the aid of-frame encoding for actual-time stereo video streaming.

关键词： Video coding Stereo image processing Video sequences Streaming media parallel processing Encoding Synchronization Low latency communication Streams Videoconferences

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Performance Model of HPC Application On CPU-GPU Platform* 2

Performance Model of HPC Application On CPU-GPU Platform*

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2nd IEEE Mysore Sub Section international conference, MysuruCon 2022

作者： Chandrashekar, B.N. Aditya Shastry, K. Manjunath, B.A. Geetha, V. Nitte Meenakshi Institute of Technology Department of Ise Bengaluru India Reva University School of Management Bengaluru India

ISBN: (数字)9781665497909

ISBN: (纸本)9781665497909

In recent years, the world of high-performance computing has been developing rapidly with enormous efforts in the integration of information technology and research. The emergence of CPU-GPU platform computing has made this possible in a very efficient manner. Nowadays, the graphic processing unit (GPU) delivers much better performance than the CPU, because of a few cores with lots of cache memory on the CPU that can handle a few software threads at a time. In contrast, a GPU is composed of hundreds of cores that can handle thousands of threads simultaneously. The CPU-GPU hybrid platform is becoming increasingly important in high-performance computing (HPC) domains such as deep learning, artificial intelligence, etc., because of its tremendous computing power. In this work, we have proposed a performance model to accelerate the performance of HPC applications on a hybrid CPU-GPU platform. We have tested and analyzed the proposed performance model using different HPC benchmark applications such as Merge sort and Matrix multiplication on different platforms such as sequential, OpenMP, MPI in a single system, MPI in the cluster, and CUDA. We have observed that parallel computing in a shared and distributed memory architecture gives better performance than sequential computing. After analyzing we have represented it in the terms of graphs for a better view of the results. Index Terms - hybrid computing, parallel computing, sequential computing, CUDA, MPI, OpenMP, CPU, GPU. © 2022 IEEE.

关键词： Graphics processing unit

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Optimizing Search and Sort Algorithms: Harnessing parallel Programming for Efficient processing of Large Datasets

Optimizing Search and Sort Algorithms: Harnessing Parallel P...

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Automation, Computing and Renewable Systems (ICACRS), international conference on

作者： Ipsit Maurya Subhratha Sinha M Suguna School of Computer Science and Engineering Vellore Institute of Technology Chennai

This research study investigates the impact of parallel programming techniques on the performance of searching and sorting algorithms. Traditional sequential algorithms have been the foundation of data processing for decades, but the increasing availability of parallel computing resources opens new possibilities for improving efficiency and reducing execution times. By leveraging parallel programming models, such as shared memory and distributed memory systems, this study explores how the parallelization of search and sort algorithms can enhance their speed and scalability. Through comprehensive experimentation and analysis, this study aims to provide valuable insights into the benefits and challenges of parallel programming in the context of searching and sorting algorithms.

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Evaluation of architecture-aware optimization techniques for Convolutional Neural Networks

Evaluation of architecture-aware optimization techniques for...

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Euromicro conference on parallel, distributed and Network-Based processing

作者： Raúl Marichal Guillermo Toyos Ernesto Dufrechou Pablo Ezzatti Facultad de Ingeniería Instituto de Computación Universidad de la República Montevideo Uruguay

The growing need to perform Neural network inference with low latency is giving place to a broad spectrum of heterogeneous devices with deep learning capabilities. Therefore, obtaining the best performance from each device and choosing the most suitable platform for a given problem has become challenging. This paper evaluates multiple inference platforms using architecture-aware optimizations for convolutional neural networks. Specifically, we use TensorRT and OpenVINO frameworks for hardware optimizations on top of the platform-aware NetAdapt algorithm. The experimental evaluation shows that on MobileNet and AlexNet, using NetAdapt with TensorRT or Open-VINO can improve latency up to 10 x and 5.3 x, respectively. Moreover, a throughput test using different batch sizes showed variable performance improvement on the different devices. Discussing the experimental results can guide the selection of devices and optimizations for different AI solutions.

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Computational Offloading and Caching Framework for parallel and distributed Edge Computing in Supercomputing Environments

Computational Offloading and Caching Framework for Parallel ...

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Emerging Research in Computational Science (ICERCS), international conference on

作者： Maha Noori Shakir Mariam Fadel Ali Abdalsalam Taha Hussain Ali Alaa Mohammed Sazan Kamal Sulaiman Al-Nisour University College Baghdad Iraq Department of Radiology Techniques Uruk University Baghdad Iraq Department of Medical Engineering Al Kitab University Kirkuk Iraq Department of Dental Industry Techniques Al-Farahidi University Baghdad Iraq Department of Computer Engineering College of Engineering Knowledge University Erbil Iraq

ISBN: (数字)9798331534967

ISBN: (纸本)9798331534974

Despite significant advancements in parallel and vector supercomputers over the past twenty years, the present generation falls short of expected performance benchmarks due to programming and scaling issues. This paper examines improvements in parallel processing, emphasizing how hierarchical parallelism and improved clustering algorithms might enhance the performance of contemporary supercomputers to meet user expectations. This study investigates the iHPI-KC algorithm, an enhanced variant of the K-means clustering technique that incorporates hierarchical parallelism to optimize computational offloading and cache scalability on many-core supercomputers, particularly the Sunway TaihuLight. The iHPI-KC approach integrates a novel hyper-parameter selection procedure (HPSP), providing three unique layers of parallelism: dataflow partitioning, centroid partitioning, and a combined partitioning across dataflow, centroids, and dimensions. Evaluation of datasets from the UCI repository and Kaggle demonstrates that the proposed system attains enhanced caching scalability (96.53%), computational offloading efficacy (94.53%), and adaptability (97.53%) relative to traditional models, simultaneously decreasing processing duration and improving execution velocity. This study emphasizes the prospects of hierarchical parallelism and algorithmic improvements to enhance supercomputing efficiency.

关键词： Scientific computing Multicore processing Scalability Computational modeling Clustering algorithms parallel processing Programming Supercomputers Vectors Partitioning algorithms

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